Huawei scientist warns of physical limits in AI chip scaling.

Huawei Semiconductor’s chief scientist and one of the foundational architects of the Ascend AI chip, Liao Heng, issued a warning in a recent public interview, stating that Western chip giants like NVIDIA are nearing physical limits as they pursue more powerful processors: “Expanding scale by continuously adding more compute chips and HBM will inevitably hit a ceiling. The industry is still pushing forward, but once this physical limit is crossed, a collapse will follow.” Liao compared the entire AI value chain to an “18-story pagoda,” aligning with NVIDIA CEO Jensen Huang’s “layered cake” framework, emphasizing that China must build collaborative capabilities across every layer—particularly fostering close cooperation between chip manufacturers and AI model developers. Liao also revealed that Huawei will soon launch its first smartphone chip designed under the Tau Scaling Law framework, enabled by LogicFolding technology. Once analyzed by institutions such as SemiAnalysis and TechInsights, “the world will clearly understand by the end of this year how this alternative path can help close the gap.” Tau Scaling Law is Huawei’s innovative design philosophy, which shifts focus from traditional chip miniaturization—whose inherent advantages are diminishing—to enhancing data transmission speeds between components within computing systems. Liao also praised Liang Wenheng, founder of DeepSeek, highlighting that the key to training top-tier models with minimal compute in 2025 lies in innovative model architecture design. He likened Chinese AI innovation to maximizing space in a small apartment, while Western counterparts reside in much larger villas. Liao noted that Huawei itself is developing AI chips through co-design mechanisms between chips and models to better support efficient architectures: “We must invest more effort into design, trading higher complexity for reduced computational resource consumption.”