According to ChainCatcher, material industry sources revealed on September 2 that TSMC is expected to continue using traditional micro-bump technology rather than hybrid bonding for advanced packaging connecting High Bandwidth Memory (HBM) with AI accelerators in the short term. Given the development cycles for related materials, finer-pitch micro-bumps are anticipated to remain in use through the later stages of HBM4 and into the early phase of HBM5. TSMC has requested its material and equipment partners to develop bonding and underfill solutions for micro-bumps of approximately 5 micrometers in size; suppliers in South Korea and Japan have already begun development, with mass production of 5μm-class bumps expected to commence in the second half of 2028. Currently, the bump height for third-generation extended HBM, HBM3E, is approximately 15–25μm, while HBM4 is approaching around 10μm. Japanese material suppliers have previously indicated difficulty in ensuring quality below 15μm. Reducing and refining bump sizes is driven by height limitations of HBM cubes and the demand for higher interconnection density. JEDEC specifies a maximum stack height of 775μm for HBM. In TSMC’s advanced CoWoS packaging, HBM stacks pre-assembled by GPU and memory suppliers are mounted onto silicon interposers via micro-bumps; 16-layer DRAM die stacks are completed within the HBM package by suppliers such as SK hynix and Samsung Electronics. First- and second-generation HBM used larger solder bumps, with micro-bumps becoming mainstream around the HBM3 generation. SK hynix employs the MR-MUF process, while Samsung Electronics uses TC-NCF. Hybrid bonding enables thinner and denser interconnects through direct copper-to-copper bonding, and TSMC has adopted it on its SoIC platform for logic chip stacking; however, HBM continues to use micro-bumps for interposer connections.
TSMC to Continue Using Micro-Bump Packaging for HBM Until HBM5
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Summary
TSMC will continue using micro-bump packaging for HBM in AI chips up to HBM5, according to ChainCatcher. The company is collaborating with suppliers on a 5-micron bump solution for mass production by 2028. HBM3E uses 15–25μm bumps, while HBM4 is transitioning to 10μm. Traders assessing the risk-to-reward ratio may monitor how packaging technology affects chip performance and costs. Technical analysis for crypto suggests keeping an eye on semiconductor-linked assets as HBM adoption expands.
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