IT Home, October 16: TechNews reported yesterday (October 15) that during the third fiscal quarter (July–September 2026) earnings call, TSMC’s Chairman and CEO, C.C. Wei, announced that the company has begun mass production of advanced packaging with five-times mask size, achieving “excellent” yields. He stated that, as of now, no other company besides TSMC has achieved this scale, and customers are highly satisfied with the mass production results.
IT Home note: "Mask size" can be simply understood as the area covered in a single exposure step during chip manufacturing. AI chips and high-performance computing chips increasingly rely on packaging multiple compute dies, high-bandwidth memory, and other components onto a single large substrate; therefore, larger package areas typically enable higher compute capacity, memory density, and interconnect density, but also make it more challenging to maintain yield.
Wei Zhengjia stated that TSMC is developing a 9-times mask-size package and is moving toward a 14-times mask-size configuration. In August this year, tech media Anue reported that TSMC’s 5.5-times mask-size CoWoS has entered high-volume production, with multiple AI customers achieving stable yields above 98%, some even reaching 99%. The company plans to expand CoWoS to more than 14 times the mask size by 2029.
Without directly naming competitors such as Intel’s EMIB, Wei stated that TSMC is prepared to step in if customers cannot secure sufficient advanced packaging capacity from competitors. He emphasized that TSMC’s top priority is ensuring the successful market launch of customers’ products, which requires providing the best technologies and securing adequate capacity.