TSMC leads in chiplet-based co-packaged optics (CPO) for data centers, and Broadcom and NVIDIA have already shipped or sampled CPO switches based on TSMC’s technology to customers.

Article author and source: Wall Street Journal

In the current data center "co-packaged optics (CPO)" race, TSMC has gained an early lead through advancements in Broadcom and NVIDIA's products. Meanwhile, Samsung may be betting on the next phase.

On July 12, the institutional research firm PhotonCap released a field investigation report stating that CPO for switches has officially transitioned from technical validation to customer deployment.

TSMC's manufacturing and advanced packaging capabilities in this segment have already been validated by its first batch of top-tier commercial projects. However, the future battlefield will be far more complex than today’s switch CPO.

When optical I/O (optical interconnect interface) penetrates into the package containing heterogeneous computing chips (XPU) and high-bandwidth memory (HBM), whoever leads the co-design of these three components will reshape the competitive landscape of the entire industry.

On July 9 at Nano Korea, Samsung Electronics Senior Vice President Won-Kyoung Choi stated that the company is developing 2.xD advanced packaging aimed at integrating HBM, logic chips, and silicon photonic chips into a single package—a direction targeting optical I/O for future AI computing packaging.

Currently, TSMC is leading the "switch CPO" market.

In today’s CPO market, TSMC is the undisputed leader.

Research shows that Broadcom has begun sampling its 102.4 Tbps CPO Ethernet switch based on TSMC’s COUPE (Compact Universal Photonic Engine) platform to early customers.

Meanwhile, NVIDIA’s Quantum-X photonic switches have begun shipping, and the Spectrum-X Ethernet photonic switches have entered production, with early adopters including CoreWeave, Lambda, and Oracle.

A common feature of this generation of products is that the optical engine is deployed near the switch ASIC (application-specific integrated circuit). The core manufacturing foundation is TSMC’s mature silicon photonics technology and SoIC 3D stacking capability.

Under this architecture, the focus of competition lies in stacking and bonding photonic integrated circuits (PICs) with electronic integrated circuits (EICs), and integrating them with the switch package. At this stage, HBM is not a necessary component.

In comparison, Samsung’s publicly disclosed “turnkey CPO solution” roadmap targets 2029. Based on current CPO switch shipment volumes and customer validation, Samsung has not yet achieved a commercialization pace on par with TSMC.

Power consumption anxiety is driving optical engines closer to computational chips.

The primary driver for moving optical I/O from traditional board-level to within the package is energy consumption.

Samsung Foundry's presentation materials for OECC 2026 reveal a key milestone:

• When pluggable optical modules are deployed at the board level, the energy consumption per bit is approximately 10 pJ;
• When the optical engine is placed on a substrate near the switch, energy consumption drops to approximately 5 pJ;
• If optical I/O is further integrated into the interposer near the XPU, power consumption can be significantly reduced to approximately 2 pJ.

The core logic behind this change is "reducing the distance over which electrical signals travel." The closer the optical engine is to the computing chip, the shorter the electrical link, and the less signal conditioning is required to compensate for losses in board traces and connectors.

Therefore, advanced packaging has become a critical step in converting "physical power advantages" into "commercial product advantages." This does not mean that CPO will immediately replace pluggable optical modules; both will coexist long-term, serving different transmission distances and power budgets.

However, Samsung's data projections reveal a trend: the pluggable optics market is growing at an annual rate of over 25%, while the CPO market is growing at an annual rate of more than 150%. Capital and R&D resources are pouring rapidly into highly integrated optical architectures.

Two CPO architectures: Samsung and TSMC’s differentiated competition

Confusing “switch CPO” with “XPU-HBM optical I/O” seriously underestimates the complexity of the next phase of competition. In fact, these are two entirely different architectures:

The first type is the current mainstream "CPO for switches." The optical engine is placed next to the switch ASIC, as seen in products from Broadcom and NVIDIA. It addresses interconnect power consumption and signal integrity issues in high-bandwidth switching scenarios. TSMC’s competitive advantage lies in silicon photonics, advanced bonding, and switch packaging integration.

The second type is an optical I/O package designed for the “XPU-HBM system.” Its architecture integrates the XPU (or GPU), HBM, and an optical engine containing PIC and EIC on a substrate. In this configuration, optical I/O is no longer a peripheral component of the switch but becomes an integral part of the “compute package.”

Samsung executives recently proposed the 2.5D advanced packaging solution, which aims to integrate HBM, logic chips, and silicon photonic chips within a single package, while expanding system-in-package capabilities through a panel-level redistribution layer (RDL) interposer to meet the massive bandwidth demands of AI data centers.

For investors, the competitive logic of these two architectures is fundamentally different: the former tests single manufacturing and packaging processes, while the latter requires deep co-optimization of computing, memory, optics, and packaging from the earliest design stages.

Samsung's trump card and the practical constraints of multi-die yield

Samsung's greatest potential differentiator lies in its "triple-play" business portfolio, which encompasses HBM, logic chip foundry, and silicon photonics platforms.

TSMC, although possessing leading-edge logic foundry, silicon photonics, and CoWoS packaging capabilities, does not produce HBM itself.

Samsung has already connected HBM with its foundry capabilities through the SF4 base die and established its own silicon photonics platform. This means Samsung can theoretically co-design the HBM interface, logic I/O, optical engine, and thermal management internally, without relying on external memory suppliers.

2.xD packaging faces an extremely stringent "multi-die yield" challenge. When the logic chip, HBM, PIC, EIC, and interposer are all integrated into a single package, the failure of any single component results in the entire expensive package being scrapped.

The increase in the number of chips, the expansion of packaging area, and the rising complexity of bonding are exponentially amplifying yield pressure and cost risks.

Meanwhile, competitors have not been idle. TSMC is advancing the integration of COUPE with CoWoS packaging to connect HBM through a mature external ecosystem.

On the other hand, storage giant SK Hynix is also aggressively expanding its advanced packaging capabilities. Its $3.87 billion advanced packaging facility in Indiana, USA, is set to begin mass production in 2028, and the company has already incorporated CPO into its memory system R&D roadmap.

Cross-domain collaboration among optics, memory, and packaging is becoming a shared focus across the entire industry chain.

Orders are the only standard that determines victory or defeat.

TSMC has won the first round of the switch CPO battle, with its advantage built on actual customer sampling, product shipments, and mass production progress.

Meanwhile, Samsung is betting on the next battle: aiming to leap ahead in AI computing packaging by leveraging its vertical integration capabilities in HBM, logic, and silicon photonics.

However, the market should not equate a "technology roadmap" with a "business moat."

Over the next 12 months, the single most important signal to watch in the industry is whether a named customer will place a design order explicitly requiring HBM, logic chips, and optical I/O to be bonded together in a single package and manufactured by Samsung.

If this order is executed, Samsung's "trinity" will transform from paper assets into a genuine business advantage.

If delivery continues to be delayed, TSMC’s flexible path, built on its leading process technology and an external HBM ecosystem, will remain the most reliable choice for AI giants.