ChainCatcher report, according to Taiwan’s Commercial Times on September 14, as GPU and ASIC computing power continues to advance, traditional copper interconnects are nearing their limits in power consumption and signal transmission. TSMC is accelerating its deployment of co-packaged optics (CPO). Industry analysts believe that if CPO bandwidth continues to double every two years, it could establish an “CPO Moore’s Law” for the AI era. Analysis suggests three primary pathways for CPO bandwidth upgrades: increasing single-lane speed from 200G to over 400G, expanding the number of optical channels from 16 to 32 or more, and adopting wavelength division multiplexing (WDM). By 2040, theoretical bandwidth could reach approximately 128 times current levels; based on today’s ~3.2T benchmarks, this suggests long-term potential to scale into hundreds of terabits. TSMC’s role in optical interconnects has expanded from pure foundry services to system integration, progressively integrating computation, HBM memory, and high-speed I/O through technologies such as 3DFabric, CoWoS, SoIC, silicon photonics, and CPO. When high-speed electrical signals exceed 200G, signal degradation intensifies over longer copper paths including ABF substrates, PCBs, and connectors—prompting the industry to shorten copper traces and extend optical paths. In terms of packaging architecture, optical engines are currently deployed on substrates; the next step may involve placing CPO on interposers, with future possibilities of using SoIC technology to enable 3D vertical integration of photonic integrated circuits (PICs) with ASICs. Industry participants note that achieving mass production of CPO still requires overcoming challenges in packaging, optical coupling, and testing.
TSMC Accelerates CPO Layout, Industry Eyes New 'CPO Moore's Law'
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Summary
TSMC is intensifying its efforts in co-packaged optics (CPO) as industry trends indicate rising demand for higher bandwidth. With copper approaching its limits, CPO could follow a new "CPO Moore’s Law," doubling in performance every two years. Bandwidth upgrades may be achieved through 400G+ channels, increased optical lanes, and WDM. By 2040, speeds could reach hundreds of Tbps. TSMC is integrating CPO with 3DFabric, CoWoS, and silicon photonics. New token listings on exchanges may reflect this shift in hardware innovation. Packaging and testing remain key challenges for mass production.
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