BlockBeats news, on June 23, analyst Damnang stated in an article posted on June 22 that JEDEC’s newly released SPHBM4 standard does not make DRAM faster, larger, or cheaper, but rather changes how HBM connects to the GPU. Traditional HBM4 requires connection to the GPU through a silicon interposer, while SPHBM4 aims to allow HBM to bypass the silicon interposer and connect directly to the organic package substrate.
The technical core of SPHBM4 is the reuse of HBM4's DRAM stack, with only the bottommost base die redesigned. Traditional HBM4 features 2,048 data signal pins, requiring a silicon interposer to manage the extremely dense pitch; SPHBM4 reduces the pin count to 512 and achieves a fourfold increase in per-pin speed through 4:1 serialization, theoretically maintaining bandwidth close to that of HBM4.
Damnang believes the key to this standard lies not in "cheap HBM," but in freeing up advanced packaging capacity. Although HBM is expensive and scarce, silicon interposers and CoWoS are equally critical bottlenecks in AI accelerator shipments. If HBM no longer occupies interposer area, the same interposer wafer capacity could support more packaged shipments.
The article estimates that in high-end AI accelerators, the HBM may occupy nearly half of the silicon interposer area. If this area were removed, the number of packages supported per wafer could theoretically increase by a factor of 1.5 to 2. However, the actual impact will depend on adoption rates, yield, product configurations, and the remaining interposer area on the GPU side.
Therefore, what SPHBM4 truly unlocks is production capacity, not per-chip cost. Even if similar technologies can reduce packaging costs by 22% to 40%, this represents only a single-digit percentage of the total cost of an AI accelerator. More important than saving hundreds of dollars per chip is the potential increase in GPU and ASIC output once production bottlenecks are lifted.
The beneficiaries may not be immediately obvious. In the short term, even if a cloud provider or chip company adopts SPHBM4 first, the released CoWoS capacity could be reallocated by TSMC to other customers on the waiting list, with NVIDIA still being the most capable of absorbing the additional capacity. For cloud providers developing their own ASICs, the value of SPHBM4 is more long-term: reducing reliance on large silicon interposers and increasing design and shipping flexibility.
The value chain will also shift accordingly. Damnang said that SPHBM4 will move the technical burden from the substrate and silicon interposer to the base die’s high-speed logic design. As per-pin speed increases, the PHY, SerDes, clock recovery, equalization, and error correction circuits will become more critical. The focus of HBM competition may shift from “who can stack higher” to “who can better optimize the underlying logic.”
At the corporate level, Samsung holds a vertical integration advantage due to its simultaneous capabilities in memory, advanced logic fabrication, and packaging; SK Hynix and Micron rely more heavily on TSMC’s advanced nodes to produce complex base dies; even amid shrinking interposer areas, TSMC retains control over CoWoS and base die manufacturing; Intel, with its EMIB, high-speed interconnects, and advanced packaging capabilities, emerges as a potential wildcard.
However, SPHBM4 is currently in the "standard released, awaiting adoption" phase. Next, we need to observe three things: which memory manufacturer will be the first to launch SPHBM4 products, whether major cloud providers will incorporate this design into their custom ASICs, and whether JEDEC will publicly release the full technical specifications.
Damnang is an analyst with a long-standing focus on semiconductors and AI infrastructure. His Substack primarily publishes analyses on semiconductors, memory, advanced packaging, foundry services, and the AI chip supply chain, characterized by breaking down complex engineering issues into industry logic accessible to investors.