SemiAnalysis teardown reveals SMIC's N+3 process matches TSMC's N6 density.

Article by: Tide Research

For decades, TechInsights has dominated the field of semiconductor reverse engineering. Last weekend, Dylan Patel’s SemiAnalysis officially released its first public teardown report from the STEEL Lab (Teardown Engineering & Evaluation Lab), targeting one of the world’s most closely watched chips: Huawei’s Kirin 9030 Pro, built on SMIC’s most advanced N+3 process.

The timing is intriguing. TechInsights is being sold to a private equity firm, while SemiAnalysis’s revenue has already surpassed this established giant. Dylan chose this moment to strike, releasing a highly technical teardown report accompanied by real photos of chips taken at an Oregon lab.

The report’s headline is a bombshell: SMIC’s N+3 process has a minimum metal pitch (M0 pitch) of just 32.5nm, smaller than Intel’s latest 18A process used in the Panther Lake processor, which is 36nm.

Without EUV lithography machines, SMIC has achieved a metal pitch finer than Intel's?

If viewed solely by its title, this message would be enough to send the entire semiconductor industry into an uproar—but SemiAnalysis itself cooled things down in the second paragraph of its report, calling it a "cherry-picked metric," a deliberately selected indicator.

This article will break down and explain this analysis report for you,

SMIC's N+3 process has indeed matched TSMC's N6 in transistor density.

The STEEL laboratory measured the Bohr density of N+3 at 113.4 MTr/mm² via TEM (transmission electron microscopy) cross-sectional analysis, slightly higher than TSMC’s N6 at 107.7 MTr/mm². The cell height decreased from 252 nm in N+2 to 228 nm, and the contact gate pitch (CGP) was reduced from 63 nm to 57 nm. Taken together, these figures indicate that SMIC has achieved logic density comparable to TSMC’s mature 7nm node using only DUV lithography, without EUV.

What is the cost?

SMIC's M0 layer uses self-aligned quadruple patterning (SAQP), which involves patterning a single mask through four processing steps to achieve finer lines. TSMC's N6 requires only double patterning (SADP) for the same layer. Quadruple patterning means more masks, stricter overlay accuracy requirements, a more complex process flow, and higher costs.

SemiAnalysis directly observed the cost of SAQP in the cross-section: the N+3 M0 trench exhibits a distinct inverse trapezoidal profile (narrower at the bottom than at the top), with a clear barrier layer enrichment zone at the trench bottom. While this morphology aids copper filling, process control becomes significantly more challenging at this 32.5nm pitch.

Think of it this way: SMIC is printing the same denomination of bills as TSMC, but each note costs several times more to produce—and carries much higher yield risk. The density is the same, but the economics are completely different.

Huawei HiSilicon's chip design capabilities are a story of another dimension.

In terms of chip area, the Kirin 9030 is nearly identical to its predecessor, the 9020 (approximately 140mm²), but it packs in more components: the CPU has been upgraded from 1 big core + 3 medium cores to 1 big + 4 medium cores, the GPU has increased from 4 to 6 compute units, and an additional Tiny core has been added to the NPU. All levels of cache have been expanded. The N+3 process density improvement enables Huawei to fit more logic units into the same chip size.

In terms of performance, the STEEL Lab cites publicly available benchmark data to clearly position the Kirin 9030: its GPU performance (Maleoon 935) is roughly on par with flagship chips from 2022, achieving a 70% improvement over the previous generation in 3DMark Wild Life Extreme scores, slightly surpassing the Snapdragon 8+ Gen 1, but still lagging behind the current flagship Snapdragon 8 Elite Gen 5 by a factor of 2.4 to 2.6 times.

The CPU situation is even more telling. The big core, TaiShan Prime, has an IPC roughly on par with the Arm Cortex-X2, a 2021 design. Apple’s M1 Firestorm core, released in 2020, still leads by 35%. The latest Apple M5 P-core outperforms it by 60% in IPC, with an absolute performance advantage of 2.7 times.

The root of the gap lies not in design, but in manufacturing. Apple and Qualcomm use TSMC’s N4 and N3P processes, which offer inherent advantages on the voltage-frequency curve: more transistors can be packed into the same area, and higher frequencies can be achieved at the same power consumption. Huawei’s core design capabilities are on par with the previous generation of industry leaders, but it is constrained by manufacturing processes that are two generations behind.

The most forward-looking part of the report is Huawei's presentation of the τ scaling law and the LogicFolding roadmap at the 2026 ISCAS conference.

Traditional semiconductor scaling has advanced on a two-dimensional plane: making transistors smaller and metal wires thinner. Over the past several decades, Moore’s Law has essentially been about this. Huawei’s newly proposed τ-scaling shifts the optimization focus from the spatial domain to the temporal domain, with the core goal of reducing the time cost of data movement and processing—including transistor switching delay, signal propagation delay, and latency in computation and storage.

LogicFolding is the engineering implementation of this theory. Simply put, it involves splitting a single logic module into upper and lower layers, stacking them face-to-face, and connecting them through ultra-fine-pitch hybrid bonding. The direct benefit is a reduction in the length of the longest signal paths. In modern chips, a significant portion of power consumption and latency is spent driving long interconnects and relay buffers. By vertically folding the logic, critical paths become shorter, enabling higher frequencies and lower power consumption.

Huawei has outlined an aggressive roadmap: the big cores of the Kirin 9030 operate at 2.75GHz, with lab samples already achieving 3.39GHz, targeting 5GHz by 2031, while using 3D stacking to push equivalent density to 295 MTr/mm², matching TSMC’s 14A node.

SemiAnalysis remains cautious. They note that Huawei’s method of calculating density differs from traditional foundries: the density of 3D stacking is calculated based on package area, and stacking multiple layers of active logic naturally results in a higher number. If the same method were applied to AMD’s MI450X (N2 top layer + N3P bottom layer), the theoretical density would reach as high as 460.2 MTr/mm²—far exceeding Huawei’s target for 2031.

But the direction itself is worth serious attention. By taking this path, Huawei is essentially shifting the work of a foundry to a system design company, under constraints on process technology. AMD’s V-Cache performs 3D stacking on cache, and the AMD MI350X moves I/O and interconnects to the bottom chip; Huawei aims to go even further by splitting the same logic block and distributing it vertically—an engineering challenge of an entirely different magnitude.

SemiAnalysis’s final conclusion is straightforward: export controls have not halted China’s chip progress, but they have altered the path and cost of that progress.

SMIC’s N+3 process demonstrates that N6-level logic density can be achieved without EUV. However, this path comes with higher costs, greater process complexity, and more challenging yield control. As you go further down this route, the marginal difficulty increases at each step: more masks, stricter overlay accuracy, and more expensive multi-patterning. Theoretically, N+4 could reach 137.8 MTr/mm² (comparable to TSMC’s N5), and N+5, if incorporating backside power delivery, could approach Intel’s 18A HP library. Yet each step becomes progressively harder, more expensive, and offers less margin for error.

Meanwhile, SMIC’s N+2 and N+3 processes are being transferred to Hua Hong, and design companies such as Alibaba’s Pingtouge and Cambricon may also benefit. The spread of chip manufacturing knowledge from a single foundry to the broader ecosystem further dilutes the effectiveness of sanctions targeting individual companies.

On the design side, Huawei and Peking University are already developing a domestic EDA tool prototype for LogicFolding. This does not equate to replacing the full toolchains of Synopsys and Cadence, but domestic EDA is evolving toward "architecture-process-packaging co-optimization."

An interesting detail: STEEL’s teardown revealed that the DRAM in the Kirin 9030 Pro comes from Samsung (K4L2E165YD, LPDDR5X-9600, 1a process node), while the 16GB Pro Max variant features packaging from both Samsung and CXMT (ChangXin Memory Technologies). The CXMT chips are labeled with a production date of week 45 of 2025 and have a process density comparable to the industry’s 1z node. This indicates that Chinese memory chips have now entered Huawei’s flagship supply chain, despite still lagging one to two generations behind Samsung and SK Hynix in process technology.

For investors, the real signal to watch is whether Huawei’s 3D stacking roadmap can enable Chinese-made chips to reach a sufficient performance threshold in applications such as smartphones, AI inference, and networking equipment, while keeping costs under control.

Once sufficient supply is established, the strategic value of this supply chain will be revalued.