SemiAnalysis reveals that SMIC's N+3 node matches TSMC's N6 density without EUV.

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Guest: Dylan Patel, Founder of SemiAnalysis

Host: None (solo narration video)

Podcast source: SemiAnalysis

Did China just surpass Intel?

Broadcast date: July 20, 2026

Disclosure: This video is an analysis of the first public report from SemiAnalysis’s STEEL teardown lab, directly promoting their paid teardown services. SemiAnalysis is in direct commercial competition with the established teardown leader TechInsights (which is currently being sold by private equity, and whose revenue has been surpassed by SemiAnalysis). The content below faithfully presents their technical analysis and does not reflect the views of this publication.

SemiAnalysis sliced open Huawei’s latest flagship chip, the Kirin 9030, and measured the narrowest metal line width under an electron microscope. The result was surprising: SMIC’s third-generation 7nm process, N+3, achieves a minimum metal pitch of just 32.5 nanometers—narrower than the 36-nanometer pitch used by Intel’s latest 18A process on Panther Lake. A Chinese foundry cut off from EUV lithography machines has surpassed Intel’s leading node in wiring density.

But SemiAnalysis itself warned in its report that this figure was deliberately selected. The N+3 does match TSMC’s N6 in transistor density, but at the cost of quadruple patterning, more masks, higher costs, and lower yields; its performance and power efficiency have fallen further behind—the Kirin 9030 is likely only comparable to Android flagships from three years ago. In short, Chinese chips are still years behind, but being behind doesn’t mean being blocked. Export controls haven’t stopped China—they’ve just changed the question. The final line in the video is most worth pondering: China doesn’t need to catch up to TSMC; it just needs to become good enough to no longer need TSMC at all.

Regarding that amazing headline number

• A Chinese wafer fab, cut off from advanced tools and without EUV, has achieved a wiring density approximately 10% tighter than Intel’s leading EUV node.
• Minimum metal spacing is only one aspect of density and does not indicate how fast logic switches operate or how much power they consume.
• This number is real, but what it measures doesn't determine who wins.

How can EUV-level density be achieved without EUV?

• EUV lets you print a detailed pattern with roughly one shot. Without EUV, you need to be more creative.
• Each additional pass adds another layer of protection, another alignment, and another opportunity for error, increasing costs and reducing yield.
• SMIC did indeed use brute force to achieve EUV-level density with DUV, but at the cost of more masks, more steps, and a higher likelihood of failure. This isn’t a draw.

Regarding density parity and performance lag

• The line became thinner, the density increased, but the physical nodes didn't keep up.
• Apple’s small efficiency cores outperformed Huawei’s large cores in integer performance, using just 1 watt, while Huawei’s large cores consumed 4.5 watts.
• SMIC is pursuing the wrong dimension.

About why people are still afraid of China

• Being years behind is different from being completely stuck.
• You can keep climbing the wall, but it will only get steeper.
• Export controls have not stopped China; they've simply changed the problem China is solving.

About the real decisive factor

• China doesn’t need to become TSMC to be meaningful. They just need to be good enough to no longer require TSMC at all.

Currently, the semiconductor manufacturing world is divided into two groups: those with EUV lithography machines and those without. Losing access to EUV is clearly a disadvantage for China, but how significant is this manufacturing gap?

This is a HiSilicon Kirin 9030, the chip inside Huawei's latest flagship smartphone. A few weeks ago, SemiAnalysis sliced it open and placed it under an electron microscope to measure the finest internal wires—the metal pitch. What they found was surprising.

The minimum metal spacing in the Kirin 9030 is only 32.5 nanometers, smaller than that of Panther Lake, which uses Intel’s brand-new 18A node. A Chinese foundry cut off from access to the most advanced tools and without EUV has achieved a wiring density approximately 10% tighter than Intel’s leading EUV node.

In this video, we’ll clarify three things: how SMIC achieved its results without EUV; why finer lines don’t always mean better performance; and why, despite being years behind, China has become a significant player on the wafer manufacturing table.

Let’s start by talking about where these numbers and measurements come from, because that’s pretty cool in itself.

SemiAnalysis has established a teardown lab called STEEL, short for SemiAnalysis Teardown Engineering and Evaluation Lab. Teardown, as the name suggests, involves physically disassembling the world’s most advanced chips to reverse-engineer how they were made. For roughly the past two decades, only one company could scale this process—but that’s no longer the case.

So everything you see next—cross-sections, line widths, transistor counts—comes directly from STEEL.

The chip lying on the "operating table" is the Kirin 9030, Huawei's flagship SoC, built on SMIC's third-generation 7-nanometer process, internally codenamed N+3, and currently China's most advanced process.

But a single number alone is meaningless without a reference. So STEEL also disassembled another chip—the MediaTek Helio G99, a low-cost smartphone SoC manufactured using TSMC’s N6 process. The reason is simple: TSMC’s N6 and SMIC’s 7nm N+3 are roughly at the same node level. One was made with the best Western equipment, the other in China under export controls. Placing both under the same microscope, the results should hopefully tell the full story.

Don’t rush to compare with the Intel 18A headline—first, look at N+3 versus N6. Has SMIC’s N+3 achieved a smaller metal pitch than N6? The simple answer is yes.

The minimum metal spacing measured inside the Kirin 9030 is 32.5 nanometers, while the finest metal spacing on the Helio G99 based on N6 is 40 nanometers—a significant difference.

But "finer lines" refers to density—how many logic gates can fit into a square millimeter—and does not directly indicate the overall quality of the chip or node. Minimum metal spacing is only one part of the equation; it does not reveal how fast the logic switches operate or how much power they consume.

In terms of density alone, SMIC has indeed achieved this. The N+3 node has approximately 113 million transistors per square millimeter, while TSMC’s N6 has about 108 million. So yes, SMIC’s latest DUV node truly surpasses the density of an EUV node.

Without EUV, how do you achieve EUV-level density? There are two methods, each with its own cost.

The first technique is multiple patterning. EUV allows you to print a relatively fine pattern in one shot. Without EUV, you need to be more creative: start by printing a coarse pattern, deposit a thin spacer along the edges, then etch away the original material, using the spacers as a brand-new, finer mask. It’s like drawing a line, tracing both edges to create two finer lines, and repeating the process. Doing this once is called Self-Aligned Double Patterning (SADP)—“self-aligned” because the spacers naturally form along the existing pattern. Doing it twice results in Quadruple Patterning (SAQP). SMIC’s finest layers require this quadruple version.

Each additional pass adds another layer of protection, another alignment, and another opportunity for error—increasing costs and reducing yield. "You know I don't like low yields."

The second approach is DTCO, or Design and Technology Co-Optimization. This means treating chip design and manufacturing processes not as separate issues, but optimizing them together. In practice, this involves compressing the cell layout itself: using fewer fins per transistor, placing the gate contact directly above the active gate instead of offsetting it to one side, or reducing the isolation spacing between adjacent cells.

Each DTCO technique recovers a bit of area, but each also makes transistors more fragile and harder to model. So SMIC has indeed matched TSMC’s EUV node in density, but by brute-forcing DUV with more masks, more steps, and a higher risk of failure. This isn’t a tie.

The density looks impressive, but that’s also where it starts to fall apart—because area is the easiest dimension to change, while power consumption and performance are much harder to optimize.

Since Dennard scaling ceased to hold in the mid-2000s, the old rule named after Robert Dennard—that shrinking transistors leads to faster, more power-efficient performance—has ended. That era of free scaling is over; with DTCO, speed and efficiency must now be pursued separately, and you can’t have both.

This is exactly what can be seen on the SMIC N+3 node. The Kirin 9030 Pro is a relatively dense chip, but its performance is roughly equivalent to that of an Android flagship from three years ago. Compared to today’s best from Apple, Qualcomm, MediaTek, and Samsung, it’s simply not in the same league. The efficiency gap is even larger than the performance gap.

The most classic example is Apple’s tiny efficiency cores—truly small ones. Apple’s E-cores outperform Huawei’s large prime cores in integer performance while consuming only about 1 watt, whereas Huawei’s prime cores consume 4.5 watts. On a per-clock basis, Huawei’s prime core is roughly on par with Arm’s Cortex-X2 design from 2021. To be honest, that’s quite respectable engineering. But Apple’s M1 from 2020 delivered about 35% higher per-clock performance at similar power levels. And today’s leading-edge designs are several generations ahead of both.

So N+3 has a slight density advantage over TSMC’s N6, but N6 is already a node from several years ago. Apple and Qualcomm are already producing chips on N4 and N3—denser nodes with far superior voltage-frequency characteristics. Chips based on N2 are set to arrive later this year. Their transistors are more numerous and switch faster at lower power. SMIC appears to be chasing the wrong dimension: while lines have become finer and density has improved, the underlying physics of the node has not kept pace.

Comparing N+3 with Intel’s latest 18A highlights the contrast more clearly. On paper, 18A can achieve a M0 metal pitch of 32 nm, matching N+3. However, in Panther Lake, Intel extensively uses high-performance cells, relaxing the metal pitch to 36 nm.

As designed, a more relaxed M0 pitch also brings cost and yield benefits by reducing complexity. However, this assumes you have the freedom to decide where and how to scale—meaning that while the headline “finer than Intel” is technically true, it doesn’t convey competitiveness. The numbers are accurate, but what they measure doesn’t determine who wins.

In terms of transistor density, 18A clearly outpaces N+3, even with slightly looser metal pitch. This is because chip design isn't just about density, and density isn't just about M0 metal pitch. Backside power delivery allows you to reduce the front-side metal pitch, since power connections enter from the back of the chip.

So why are people still afraid of China? Because falling behind by a few years is not the same as being completely stuck.

SMIC still has room for growth on DUV. Finer lower-level metals, such as M0—which is just the first metal layer—are followed by many additional layers. Shorter cells and tighter gate pitches are also possible. On paper, future N+4 could approach TSMC’s N5-level density, and N+5 with backside power delivery could reach Intel 18A-level density. But again, this is only about density—power consumption and performance will not catch up.

The key point is that difficulty is cumulative. Each individual optimization makes sense on its own, but without EUV to combine them all, each new node becomes slower, more expensive, and less forgiving than the last. You can keep climbing the wall, but it only gets steeper.

Export controls have not stopped China; they've simply changed the problem China is solving.

Moreover, knowledge is spreading. SMIC has been asked to license its N+2 and N+3 processes to other domestic wafer foundries. If this process expertise flows into AI accelerators, the choke point will no longer be a single foundry that can be sanctioned, but an entire ecosystem.

A quick review of SMIC’s 7nm N+3 node: no EUV, no backside power delivery. Higher complexity, higher cost, and a tangible efficiency gap. By every critical metric on the leading edge, China has not narrowed the gap with TSMC, Intel, or Samsung. This is clearly evident under scrutiny.

But being "behind the cutting edge" and being "irrelevant" are two different things. If domestic chips are good enough to be used in phones, inference, networking, or any security-sensitive applications, that’s a win. China doesn’t need to become TSMC to matter—they just need to be good enough to no longer require TSMC at all.

All content in the video comes from STEEL: annotations, block-level analysis, and direct electron microscope cross-sections cutting through logic and storage. The video doesn’t cover many details: the full fabrication process, material analysis, fin measurements, and package decapsulation. For a deep dive into SMIC’s latest node, check out SemiAnalysis’s teardown article—link in the video description.

This is STEEL’s first public report, and more are certainly coming. If you enjoy this type of content, subscribe. "I’d love to hear your thoughts on this—good enough to no longer need TSMC? Let me know in the comments."