Samsung Plans to Adopt High-NA EUV for 1nm Production by 2030

Samsung clearly stated at the 2026 NGL conference that it plans to adopt High-NA EUV as its primary manufacturing technology starting from the 1nm (A10) node, around 2030; prior to that, 2nm, 1.4nm, and early 1nm nodes will continue to rely primarily on 0.33 NA EUV and multiple patterning.

Article author, source: 0x9999in1, ME News



• Samsung clearly stated at the 2026 NGL conference that it plans to adopt High-NA EUV as its primary manufacturing technology starting from the 1nm (A10) node, around 2030; prior to that, 2nm, 1.4nm, and early 1nm nodes will continue to rely primarily on 0.33 NA EUV and multiple patterning.
• This is not Samsung losing interest in High-NA EUV, but rather a clear strategic retreat: High-NA can increase the numerical aperture from 0.33 to 0.55, significantly improving resolution and reducing multi-patterning, but the high cost of equipment, partial-field exposure, masks, photoresist, inspection, and yield still make it far from a simple “swap-and-upgrade” proposition.
• Samsung's biggest practical challenge is not whether it adopts High-NA early enough, but whether it can solidify 2nm yield, customer adoption, capacity utilization, and execution on 1.4nm between 2026 and 2029. Advanced equipment cannot replace mature manufacturing.
• Intel chose to shoulder the technological benefits and learning costs upfront, TSMC opted to maximize the potential of its existing 0.33 NA EUV technology, and Samsung delayed the full-scale mass production of High-NA to the 1nm node. These three companies are betting not on the same technological path, but on different capital efficiency curves.
• My assessment is that the most positive signal from Samsung’s roadmap is not “High-NA by 2030,” but rather its acknowledgment of a harsh reality: in advanced process competition, the winner is not the one who acquires the most expensive machines first, but the one who can reliably turn complex technologies into deliverable, profitable wafers.

On August 11, at the "2026 Next-Generation Lithography + Patterning Academic Conference" held in Korea, Park Chang-min, an expert from Samsung Electronics' Semiconductor Institute Foundry Process Development team, outlined a clear roadmap: the full-scale production of High-NA EUV is targeted for the 1nm node—the A10 era—around 2030. More notably, he added that Samsung originally intended to introduce High-NA EUV at the 2nm and 1.4nm nodes, but technical challenges still need to be resolved; High-NA EUV will only become truly essential at the A10 node and below. The disclosed roadmap also reveals that Samsung plans to begin mass production of SF1.4 in 2029 and advance to SF1.4+ and 1nm around 2030.

The weight of this statement outweighs that of “1nm with High-NA” itself. Looking back, Samsung’s stated goal at the 2022 Foundry Forum was to begin mass production of 2nm in 2025 and 1.4nm in 2027. Today, the first-generation 2nm has already entered mass production, but the latest publicly disclosed roadmap has pushed the 1.4nm timeline to 2029. In other words, over the past few years, Samsung’s advanced process roadmap has not accelerated as expected—it has instead undergone a realistic recalibration.

Therefore, I prefer to view today’s High-NA roadmap as a “reordering” rather than another technological declaration. Samsung is not saying High-NA is unimportant; it’s saying this technology is too important and too expensive to be rushed solely for the sake of nominal node leadership.

The most dangerous misconception in advanced processes is equating "owning equipment" with "owning manufacturing capability." Lithography tools can be purchased, but process windows, defect density, mask infrastructure, material formulations, measurement capabilities, PDK maturity, and customer trust cannot be bundled and delivered along with the equipment. What Samsung truly needs to prove is not merely its ability to move the most advanced equipment into the cleanroom, but its capacity to make that equipment operate reliably, stably, and economically over the long term.

High-NA EUV sounds like a lithography machine upgrade, but what it truly addresses is the growing burden of multiple patterning at advanced nodes.

Both current EUV and High-NA EUV systems use a light source with a wavelength of 13.5 nanometers; the change occurs in the numerical aperture (NA), which increases from 0.33 to 0.55. A higher numerical aperture enhances the optical system’s ability to collect and focus light, enabling the resolution of finer patterns. ASML’s EXE:5200B specification offers an 8-nanometer resolution, a significant improvement over the approximately 13-nanometer resolution of the current NXE platform. ASML also states that imaging contrast has improved by approximately 40%, allowing single-exposure feature sizes that are about 1.7 times smaller than those achievable with NXE. From a purely optical standpoint, this is precisely what makes High-NA so compelling.

Why do chip manufacturers care so much about "single exposure"? Because when features become so fine that a single exposure cannot capture them, manufacturers must split the same layer into two or more patterning steps, then reassemble them through deposition, etching, and alignment. Each additional cycle increases equipment usage, overlay error, the chance of defects, and production time.

It’s like being able to draw a line in one stroke, but now you must split it into two strokes and require the deviation between them to be as small as the atomic scale. Theoretically, it’s possible—but mass production isn’t a lab demonstration. When you’re processing tens of thousands of wafers, with dozens of critical layers, and repeating this process continuously on a production line all year, even the tiniest fluctuation eventually becomes a cost.

Therefore, the value of High-NA is not just about “smaller,” but about shifting part of the complex multi-patterning back into a single exposure. Reducing one process step means not only eliminating one step, but also potentially shorter cycle times, lower risk of overlay errors, and more controllable defect sources. This is why, near the 1nm node, Samsung concluded that 0.33 NA EUV would increasingly struggle to rely on multi-patterning.

But the question arises: if it’s so good, why not get started now?

The answer is simple—and not very romantic—because "more advanced" doesn't mean "cheaper per wafer."

The biggest controversy surrounding High-NA EUV has never been whether it can work, but when it will become economically viable.

Reuters previously reported that High-NA equipment costs close to $400 million, nearly double the price of existing EUV equipment; TSMC executives have also publicly stated that sufficient scaling benefits can still be achieved with existing EUV technology at nodes such as A14, making it unnecessary to immediately incur higher manufacturing costs solely for the adoption of High-NA.

Moreover, High-NA is not as simple as changing the NA from 0.33 to 0.55. To allow the larger projection optical system to continue using masks of existing dimensions, ASML adopted an anamorphic optics design with asymmetric reduction, which reduces the single-exposure field of view of High-NA to half that of current EUV systems. ASML must rely on faster wafer and mask stages to offset the throughput pressure caused by the increased number of exposures. In other words, while High-NA uses higher resolution to eliminate some of the need for multiple patterning, it simultaneously introduces new equipment, exposure field, and process integration constraints.

Further down, even more challenging aspects arise: photoresist must simultaneously achieve sensitivity, resolution, and roughness under more demanding conditions; masks and pellicles must be adapted to new optical systems; and measurement and defect detection capabilities must also be upgraded in tandem. Lithography has never been a solo performance by a single machine—it is an engineering endeavor carried out by an entire chain of materials, optics, masks, inspection, computational lithography, and process control.

So it’s not embarrassing for Samsung to say today that “further technological reinforcement is still needed.” The real danger lies in mass-producing billions of dollars’ worth of equipment for a so-called “industry first” label, despite knowing the ecosystem isn’t yet sufficiently mature—only to find that per-wafer costs have risen, utilization rates remain low, and yields haven’t improved accordingly.

Will high-NA eventually enter more advanced nodes? Based on current technology roadmaps, this is a clear trend. However, bridging the gap between laboratory capability and large-scale economic viability is not a single product launch—it’s a long manufacturing learning curve.

Here comes the most interesting part: Facing the same generation of ASML High-NA EUV, three advanced logic manufacturers are offering three entirely different responses.

Intel is the most aggressive pioneer. In 2024, it became the first to complete the assembly of a commercial High-NA system; by July 2026, ASML announced that Intel had validated High-NA process options on select Intel 18A product layers and became the first company to ship high-volume logic products using High-NA technology. It is important to note that this does not mean Intel 18A fully relies on High-NA; Intel’s deeper integration of High-NA at the process design level will also include subsequent nodes such as Intel 14A.

Why is Intel willing to bear these costs so early? Because what it lacks isn’t just process capability, but the time needed to rebuild its competitive edge in advanced manufacturing. For a challenger aiming to strengthen its foundry business, gaining early experience with High-NA equipment, process data, and engineering talent years in advance is itself an asset. Even if initial unit costs aren’t favorable, these learnings could provide a strategic advantage for the 14A node and beyond.

TSMC’s logic is almost the opposite. It doesn’t need to prove itself by being the first to adopt High-NA. As long as 0.33 NA EUV combined with multiple patterning can still enable the A14 to meet its performance, power, density, and yield targets, TSMC has ample reason to continue maximizing the return on its existing equipment. What TSMC truly cares about is not how advanced a single machine is, but how many deliverable wafers each dollar of capital expenditure ultimately generates.

Samsung stands between the two. It doesn’t have Intel’s imperative to secure early device learning curves, nor does it have TSMC’s massive market share as a buffer. Therefore, positioning the full-scale production node for High-NA at 1nm is a very practical compromise: conducting R&D now, accumulating data, and co-developing with the supply chain, while deferring major capital commitments until the technology and economics are clearer.

This is not mere conservatism, but the restraint that Samsung particularly needs right now.

If we talk only about technology, it's easy to overlook a more harsh reality: Samsung's discussion of 1nm today is not taking place on an even playing field.

According to TrendForce data, in the first quarter of 2024, TSMC held approximately 61.7% of the global wafer foundry market share, while Samsung held about 11%; by the first quarter of 2026, TSMC’s share increased further to around 72%, while Samsung’s declined to 6.5%. During the same period, demand for advanced nodes continued to concentrate among leading players, driven by AI GPUs, xPUs, and server CPUs.

Over two years, one metric rose from over 60% to more than 70%, while the other fell from double digits to single digits. This is the most unavoidable fact when interpreting Samsung’s High-NA roadmap.

The real issue Samsung needs to address is never whether it has achieved 1nm, but why customers would entrust it with producing a flagship chip critical to their multi-year product cycles. The answer lies not in node names, but in yield curves, on-time delivery, PPA realization, production stability, EDA ecosystem, IP library, packaging collaboration, and commercial terms.

Samsung has already been making progress in this direction. Official disclosures indicate that first-generation 2nm products began mass production in the fourth quarter of 2025, with second-generation 2nm products set to expand further in 2026, while development of 1.4nm technology continues. Samsung is also increasing its business scale at advanced nodes by incorporating 2nm GAA, HBM-based die, advanced packaging, and design wins with AI/HPC customers.

But this also means that the real pressure window will be from 2026 to 2029.

1nm is a distant goal, 2nm is the business at hand, and 1.4nm determines whether Samsung can still regain its customers’ trust in its advanced process roadmap. If 2nm fails to consistently convert customers from pilot orders to volume orders, and if 1.4nm experiences another significant delay, then even if High-NA equipment arrives on schedule by 2030, it will be difficult for Samsung to automatically return to a leading position.

Photolithography can reduce manufacturing complexity, but it cannot replace customer relationships; equipment can improve resolution, but it will not directly increase market share.

AI is pushing this lithography race in a somewhat contradictory direction.

On one hand, AI chips require higher transistor density, better energy efficiency, larger caches, and more complex interconnects, significantly increasing the value of advanced processes. TrendForce estimates that, driven by AI-related demand, global foundry revenue could rise by approximately 24.8% year-over-year in 2026, reaching about $218.8 billion. Advanced nodes and advanced packaging are attracting an increasing share of capital.

On the other hand, AI chips themselves are becoming increasingly expensive. If an advanced node leads to significantly higher costs due to equipment depreciation, process transitions, and low initial yields caused by High-NA, customers will not perceive it as “more advanced”—they’ll see higher wafer quotes. AI customers have money, but they’re not without calculators.

This is also the true commercial inflection point for High-NA: only when the cost of multiple patterning required to continue using 0.33 NA EUV exceeds the depreciation and process transition costs of High-NA will it truly become an economic, not just technological, advancement.

Samsung is betting on the inflection point around 1nm, and I believe this logic holds. At that scale, the complexity of critical layer patterns, overlay tolerances, and manufacturing cycles will face greater pressure, and the marginal cost of continuing to stack multiple patterning will keep rising. Only with High-NA’s single-exposure capability is there a better chance to recoup the high equipment investment through process simplification.

But there are no guarantees here. By around 2030, the maturity, throughput, and supply of ASML equipment, the maturity of the photoresist and mask ecosystem, and competitors’ advancements in low-NA multiple patterning will all change the equation.

So what Samsung announced today is not an answer, but a bet with very specific conditions.

The semiconductor industry easily creates an illusion: the smaller the node, the more advanced; the more expensive the equipment, the more powerful; whoever announces first leads the pack.

The real world is far more complex. The hardest part of advanced manufacturing has never been developing a technology, but turning it into an industrial process that remains stable when repeated thousands of times daily, inspires customer confidence to place orders, and is financially profitable.

From this perspective, Samsung’s decision to delay full-scale production of High-NA to 1nm does not inherently mean it is “falling behind.” On the contrary, if it can leverage the period from 2026 to 2029 to deepen its multi-patterning capabilities with 0.33 NA EUV, truly scale up yield and customer base for 2nm, deliver 1.4nm according to the revised timeline, and simultaneously complete material, mask, metrology, and process integration for High-NA ahead of schedule, the transition in 2030 will be far more valuable than a rushed launch aimed at nominal technological leadership today.

But the risks are equally clear: if Samsung continues to lose market share in advanced foundry over the next three to four years, if 1.4nm is delayed again, and if the customer ecosystem further consolidates around TSMC, then “full adoption of High-NA by 2030” could shift from a proactive choice to a reactive catch-up.

So, don't view High-NA as a button for Samsung to turn things around.

It’s more like an extremely sharp and extremely expensive knife. Of course, when the knife is drawn matters, but what matters more is whether the person holding it has practiced the fundamentals thoroughly enough.

What will truly matter in 2030 won’t be how many EXE machines are lined up in Samsung’s factories, but whether it can consistently produce stable 1nm wafers and earn customers’ trust to entrust it with their most critical chips again and again.

If possible, High-NA will be a crucial piece in Samsung’s effort to reapproach the center of advanced manufacturing.

If not, no matter how advanced the light, it cannot illuminate a roadmap unsupported by yield and orders.

1. ZDNet Korea: "Samsung Electronics Applies High-NA EUV Technology from 1nm Onward," August 11, 2026.
2. Samsung Electronics: "Samsung Electronics Unveils Plans for 1.4nm Process Technology and Investment for Production Capacity at Samsung Foundry Forum 2022," October 4, 2022.
3. Samsung Electronics: "Samsung Electronics Announces Fourth Quarter and FY 2025 Results," January 29, 2026; "Samsung Electronics Announces First Quarter 2026 Results," April 30, 2026.
4. ASML: “TWINSCAN EXE:5200B - EUV Lithography”; “5 Things You Should Know About High NA EUV Lithography”.
5. ASML: "High NA EUV reaches new readiness milestone with first high-volume logic product," July 15, 2026.
6. Reuters: “TSMC still evaluating ASML's 'High-NA' as Intel eyes future use,” May 27, 2025.
7. TrendForce: "Strong AI demand and early consumer electronics inventory buildup drive top 10 foundries to 3.7% QoQ revenue growth in 1Q26," June 12, 2026.
8. TrendForce: "Strong AI Momentum to Drive 24.8% Growth in Foundry Revenue to US$218.8 Billion in 2026," March 19, 2026.