Samsung Electro-Mechanics Proposes MLC Composite Solution for AI Semiconductor Substrates

ChainCatcher report: On September 10, Kim Sang-hoon, Head of the Packaging Division at Samsung Electro-Mechanics, delivered a speech at the KPCA Show International Symposium INSIGHT 2026 held at the Songdo Convention Center in Incheon, outlining the multi-layer core (MLC) technology direction to address the trends of larger and higher-layer AI semiconductor packaging substrates. Kim stated that the traditional single-layer core (SLC) approach, which increases substrate thickness by adding thicker CCL layers, leads to greater difficulty in via and circuit fabrication as the core thickens, and restricts the reduction of via size. Transitioning to MLC—combining multiple layers of CCL with PPG, or even hybrid structures of two CCL layers—can simultaneously enhance rigidity and routing flexibility, while allowing ground planes or signal traces to be placed on PPG layers. Adding an adhesive layer between two CCL layers provides more stable substrate support, but increases process complexity. Current mass production typically uses bump pitches of 90μm or greater; around 85μm represents a turning point for printed fine solder ball processes, with significant difficulty emerging near 80μm, and metal bumps potentially becoming necessary at 55–45μm scales. Glass core is another option, offering higher rigidity and lower coefficient of thermal expansion, which helps reduce warpage in large packages, but requires solutions for fragile handling and microvia plating technologies. Substrates must simultaneously meet requirements for signal integrity, power integrity, and mechanical integrity; high-performance packaging substrates are expected to evolve from approximately 20 layers and 90mm sizes toward 120mm sizes and beyond 40 layers.