Samsung Delays 1.4nm Process to 2029, Focuses on Achieving 2nm Maturity

Samsung Foundry's advanced process roadmap is undergoing a notable change.

Samsung originally planned to achieve mass production of its 1.4nm process in 2027, but this timeline has now been adjusted to 2029. In other words, before moving toward 1.4nm, Samsung will continue to expand and optimize its 2nm process, focusing over the next few years on process maturity, yield improvement, and customer adoption. Samsung first announced in 2022 that mass production of 1.4nm would begin in 2027; the delay to 2029 means this goal is now two years later than originally planned, and Samsung still needs to further refine its 2nm platform for three more years until 2029.

Samsung has previously pursued an aggressive strategy in advanced process nodes, notably being the first to adopt GAA (gate-all-around) transistors at the 3nm node, aiming to establish a differentiated advantage and close the gap with TSMC through faster node iterations. However, as the industry enters the 2nm era, the technical complexity and capital investment required for advanced processes are rapidly increasing, and competition is no longer simply about who enters the next node first.

For a foundry, whether a new process node can truly create value ultimately depends on yield, performance, power consumption, number of customers, and mass production costs. Therefore, rather than rushing into 1.4nm, it may be a more realistic choice for Samsung to first mature its 2nm platform and then extend its commercial lifecycle through various derivative processes.

In fact, Samsung is not standing still on 2nm. In addition to the standard SF2, Samsung is advancing 2nm derivative processes tailored for different applications and plans to introduce technologies such as backside power delivery in more advanced versions. For AI and HPC chips, as die sizes continue to grow and power consumption rises, the power delivery network has become a critical factor affecting performance. Therefore, what Samsung truly needs to address in the coming years is not “how to quickly develop a 1.4nm process,” but rather how to make 2nm a more mature, reliable, and scalable manufacturing platform.

It is worth noting that Samsung has not rushed to adopt High-NA EUV, or high-numerical-aperture extreme ultraviolet lithography, as a mandatory technology for mass production at the 2nm and 1.4nm nodes. Previously, Park Chang-min, Vice President of Samsung Electronics’ Technology, stated that the company aims to apply High-NA EUV to mass production at advanced nodes such as 2nm and 1.4nm in the future, but the technology still requires further maturation. Samsung believes that High-NA EUV will likely become essential for advanced node mass production starting from the A10 node and below—that is, at the 1nm level and beyond—and is currently collaborating with industry partners on joint development.

The primary advantage of High-NA EUV is that its higher numerical aperture further enhances lithographic resolution, reducing the need for some complex multi-patterning processes and enabling the fabrication of more advanced transistors. However, the challenges are equally apparent: High-NA EUV tools are extremely expensive, and their exposure field is smaller compared to conventional EUV, potentially increasing stitching requirements for increasingly large AI and HPC chips. Additionally, supporting elements such as photoresist, masks, pellicles, and computational lithography must also be upgraded in tandem. Therefore, for wafer fabs, High-NA EUV is not simply a case of “the more advanced the technology, the better”—it is a long-term investment requiring careful consideration of equipment cost, chip area, yield, capacity, and PPA benefits.

This is also one of the key reasons Samsung currently does not view High-NA EUV as a mandatory technology for 1.4nm mass production. For Samsung, if the established Low-NA EUV infrastructure can still enable the 1.4nm node, there is no need to prematurely incur the additional costs and process complexity associated with High-NA EUV solely for higher lithographic resolution. In comparison, waiting for High-NA EUV to mature further and reserving its value for 1nm and below nodes may be a more pragmatic approach.

From this perspective, Samsung’s delay of the 1.4nm node does not signify a slowdown in the race for advanced processes; rather, it indicates that the industry is entering a new phase. For over a decade, the core of advanced process competition has been “who enters the next node first”—from 28nm to 16/14nm, 10nm, 7nm, 5nm, and 3nm, the node number itself was a key indicator of a foundry’s technological capability. However, at 2nm and below, the cost of simply pursuing further node shrinkage has risen dramatically. New technologies such as GAA, backside power delivery, EUV, and High-NA EUV require massive R&D and capital investment, while the performance and density improvements delivered by each new generation may no longer match the pace seen in previous generations.

Meanwhile, the real challenge in advanced processes is no longer just “making it work,” but “making it work consistently.” Especially as the die sizes of AI GPUs and HPC chips continue to grow, larger chip areas demand higher wafer manufacturing yields. Even if a process achieves higher transistor density, if yield ramp-up is slow and wafer costs remain too high, customers may ultimately be unwilling to adopt it. Therefore, foundries now need to calculate not only how much transistor density and performance have improved, but also how many functional chips each wafer can produce, and whether customers are willing to pay a premium for these performance gains.

More importantly, the value of advanced processes is no longer solely derived from transistor scaling. Chiplets, 3D stacking, HBM, and advanced packaging are all becoming critical methods for enhancing AI chip performance. The final performance of an AI chip now depends on multiple factors, including the compute die, HBM, interconnects, power delivery, thermal management, and packaging. Therefore, competition in advanced processes in the future will fundamentally shift from a pure “node race” to a comprehensive competition involving technology, cost, and ecosystem. Samsung’s extension of the 2nm lifecycle can be seen as an effort to rebalance technological progress with commercial returns—but only if it significantly improves 2nm yield and customer adoption over the next three years.

The issue is that while Samsung has slowed down, TSMC has not paused. TSMC’s N2 process is already in mass production, and its first node beyond 2nm, A16, is scheduled to enter mass production in the second half of 2026. This means that while Samsung is still refining its 2nm family, TSMC is already moving toward the 1.6nm node.

One of the most significant changes in A16 is the introduction of TSMC’s SPR (Super Power Rail) backside power delivery technology. In traditional chips, power and signal lines are primarily concentrated on the front side of the transistor. As process nodes continue to shrink, front-side routing resources have become increasingly constrained, intensifying competition between power and signal networks and exacerbating issues such as routing congestion and IR drop. Backside power delivery relocates the power path to the back of the chip, freeing up more front-side routing resources for signal transmission while shortening the power path and reducing power impedance, thereby improving power delivery efficiency in advanced process nodes.

TSMC's data shows that, compared to N2P, the A16 can achieve an 8% to 10% speed increase at the same power level, or reduce power consumption by 15% to 20% at the same speed, with chip density improved by up to approximately 10%. This means that the significance of A16 goes beyond simply advancing the node from 2nm to 1.6nm—it further unlocks the performance potential of advanced processes through backside power delivery. For AI and HPC chips especially, as chip sizes continue to grow and power consumption rises, power integrity and signal integrity have become as critical as the transistors themselves.

In fact, backside power delivery has become a key technological direction for advanced nodes at 2nm and below. Intel has introduced PowerVia in its 18A process, TSMC has adopted the SPR scheme in its A16 node, and Samsung is also advancing related technologies. It is clear that competition in advanced nodes has expanded beyond transistor architecture to include coordinated advancements in power delivery, interconnects, design, and manufacturing processes.

Notably, TSMC had previously stated it would take a cautious approach to High-NA EUV. Given Samsung’s recent delay, TSMC has once again made the right bet.

Samsung’s 2nm roadmap over the next three years faces considerable pressure. On one hand, it must continue improving 2nm process yields and accelerating customer adoption; on the other, it must contend with TSMC’s ongoing advancements in the A16 node and subsequent, even more advanced nodes. By 2029, when Samsung finally launches its 1.4nm process, TSMC and Intel are likely to have already entered a new technological phase.

This also means that future competition in advanced processes can no longer be simply measured by numbers like “2nm, 1.4nm, 1nm.” Technologies such as GAA, backside power delivery, EUV, High-NA EUV, DTCO, and advanced packaging will collectively determine a chip’s final performance and cost. The competition in advanced processes is shifting from “who has the more advanced node” to “who can deliver cutting-edge technologies as scalable products at a more reasonable cost.”

Samsung is not abandoning 1.4nm; instead, it is using the next three years to mature, scale, and gain customer adoption for its 2nm process. But a key question arises: by the time Samsung truly moves to 1.4nm in 2029, where will TSMC and Intel be? This may be the most critical aspect of the advanced process competition.

This article is from the WeChat public account "Semiconductor Industry Watch" (ID: icbank), authored by the editorial team.