Samsung Considers Outsourcing Google TPU I/O Chip Backend Design Amid Surge in 2nm Orders

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Samsung is reportedly considering outsourcing the backend design of Google’s 10th-generation TPU I/O chip to meet growing demand for 2nm production. The chip, which is part of the altcoins to watch for on-chain data trends, features a compute processor from TSMC and an I/O chip from Samsung. Current collaboration with MediaTek is underway, with mass production expected by 2028. Samsung’s 2nm capacity is under strain due to clients including Google, Tesla, and Anthropic. Potential partners include ADTechnology, Gaonchips, and Alphachips, though the latter two are already fully occupied.
ME AI message: Samsung Electronics is considering outsourcing the backend design of the I/O chip for Google’s 10th-generation TPU (codenamed Icefish). Google’s TPU, built on a 2-nanometer process, consists of a Compute processor and an I/O chip—the former is expected to be manufactured by TSMC using a 1.4-nanometer process, while the latter will be produced by Samsung using a 2-nanometer process to handle data transmission between the Compute processor and HBM. Google is co-designing the chip with MediaTek, with mass production potentially beginning as early as 2028. However, Samsung has recently experienced a surge in 2-nanometer orders—from Google and Tesla, as well as new clients Anthropic and DeepX—leaving its internal workforce stretched thin. Previously, Samsung used its own team to handle the backend design of Tesla’s 2-nanometer autonomous driving chip. Potential outsourcing partners under consideration include ADTechnology, Gaonchips, and Alphachips. The first two are already heavily engaged in major projects—ADTechnology is focused on its 2-nanometer CPU project, ADP620, targeting annual revenue exceeding 1 trillion KRW between 2028 and 2029; Gaonchips is preparing to participate in the Korean Ministry of Trade, Industry and Energy’s approximately 800-billion-KRW K-On-Device AI project, collaborating with Hyundai Motor and others to develop 5-nanometer ADAS chips. Since backend design is essentially a low-value-added service contract (typically in the hundreds of billions of KRW range), far below the scale of full-cycle ASIC projects spanning design to tape-out (which can reach hundreds of billions to trillions of KRW), both companies are not highly enthusiastic and are only willing to take on limited work to build track records in advanced-node projects. Alphachips, however, views Google’s TPU project as a key growth driver and is more eager to participate. Industry insiders note that orders overflowed from TSMC due to its 2-nanometer capacity constraints are contributing significantly to Samsung’s workforce pressure. (Source: BlockBeats)
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