CoinDesk reports:
IT Home, October 21 — South Korean media ZDNET Korea reported yesterday that NVIDIA’s next-generation Groq LPU AI inference accelerator chip is expected to adopt a 3D-stacked DRAM solution based on TSV (Through-Silicon Via) technology.
The current generation of Groq LPU employs a cache design with high-capacity SRAM to deliver fast decoding output. However, SRAM has inherent limitations in terms of smaller capacity and limited density gains from process node advancements, which constrain performance on large models and chip iterations.
IT Home noted that Cerebras, which also follows the large SRAM technology approach, has previously announced that its upcoming CS-6 will feature 3D vertical integration of DRAM.
Related reading:
- Cerebras Unveils CS-6 Wafer-Scale Evolution: Groundbreaking 3D Stacking with First-Ever Vertical DRAM Integration