NVIDIA Rubin Ultra HBM reduced to 8-Hi as bandwidth cost becomes key constraint

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Release Time: 2026/09/06 04:24:13

NVDA

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Summary

NVIDIA reduced the HBM stack in Rubin Ultra to 8-Hi, citing rising per-unit bandwidth costs as a key factor. This change cuts DRAM die usage by one-third, alleviating HBM supply pressures while maintaining or increasing total bandwidth. Altcoins to watch may experience a bullish trend as AI chip design increasingly prioritizes bandwidth efficiency over raw HBM capacity, with power and cost constraints now taking precedence.

ME AI message: SemiAnalysis states that NVIDIA has reduced the HBM stack height of Rubin Ultra from 12-Hi to 8-Hi—not primarily to lower capacity, but because the current bottleneck in AI inference is cost per unit of bandwidth ($/bandwidth), not cost per unit of capacity ($/capacity). HBM stack height primarily determines capacity, while total bandwidth depends more on the number of HBM stacks, interface width, and transfer rate. Therefore, reducing from 12-Hi to 8-Hi cuts DRAM die usage by approximately one-third, alleviating the current tight and expensive HBM supply constraints, while maintaining or even increasing overall bandwidth by keeping the number of stacks and interface configuration unchanged. This means NVIDIA is proactively trading lower HBM capacity for higher bandwidth efficiency. For AI workloads increasingly dominated by inference, models require not just “more data storage,” but also continuous, rapid movement of model weights and KV Cache—making memory bandwidth increasingly critical. The adjustment in Rubin Ultra reflects a shift in the HBM competitive landscape: AI chips are no longer focused solely on stacking higher HBM capacity, but on maximizing effective bandwidth within limited constraints of DRAM, power, and cost. The core bottleneck for HBM is shifting from “is there enough capacity?” to “how much bandwidth can I get for each dollar?” (Source: Wall Street Journal)

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