NVIDIA Launches NVHBM Memory Technology with 30% Higher Bandwidth and 15% Lower Power Consumption

ME News reports that on August 27 (UTC+8), NVIDIA unveiled NVHBM technology for next-generation AI infrastructure. NVHBM is a custom HBM base die co-designed and validated with major memory chip suppliers, and will be delivered to hyperscale cloud providers and AI-native companies developing custom AI accelerators (XPUs) via NVLink Fusion. Compared to standard HBM4e, NVHBM delivers up to 30% higher memory bandwidth per stack, reduces HBM power consumption by up to 15%, and frees up to 25% of XPU die area. NVIDIA states these improvements enable custom accelerators to support larger AI models, faster KV cache access, and enhanced training and large-scale inference efficiency. By redesigning the physical memory interface—moving the memory controller into the 3D HBM stack and integrating a custom PHY—NVHBM reduces PHY and associated area by up to 67% while simplifying interposer routing. The freed die area can be allocated to expand matrix engines, caches, networks, and other workload-specific features. At the rack level, the NVLink Fusion chiplet connects custom XPUs to the NVLink network and links CPUs via NVLink-C2C. NVIDIA states that combining NVHBM with NVLink Fusion increases end-to-end performance per XPU by approximately 30%, while enabling custom XPUs to form heterogeneous computing systems alongside NVIDIA GPUs. The official commercial release date has not been disclosed in the article. (Source: BlockBeats)