According to the Zhitong Finance app, J.P. Morgan’s latest research report noted that Micron Technology (MU.US) provided a detailed overview of its latest technological innovations and long-term strategies for its three core product lines—DRAM, HBM, and NAND—at its investor technology webinar on October 21. The firm, led by Harlan
The analyst team led by Sur believes that Micron’s technology roadmap is clear and forward-looking, positioning it to continue benefiting from the surge in AI-driven storage demand, and thus maintains its “Outperform” rating.
Maintain the 6F² DRAM architecture while concurrently advancing 3D DRAM.
JPMorgan Chase's report notes that Micron has clearly addressed the industry debate over the 6F² versus 4F² technology paths in DRAM architecture evolution. Micron stated that its next-generation DRAM node will continue to use the 6F² architecture rather than 4F². The company is confident in its ability to maintain its leadership in power efficiency and performance through rigorous node scaling, process innovations, and product-level optimizations.
Micron revealed that it has researched 4F² DRAM for approximately 20 years, but ultimately decided not to adopt it, primarily due to increased process complexity, higher costs, and the company's assessment that the scaling benefits were limited.
JPMorgan Chase's research report detailed three major challenges faced by the 4F² architecture in manufacturing: First, this architecture requires more intensive deposition and etching processes, significantly increasing the probability of yield issues; second, the 4F² architecture imposes stricter process tolerance requirements (such as overlay and alignment), placing greater pressure on manufacturability and yield; finally, the architecture itself is prone to causing "floating body effect" (Floating
Body effect, causing charge to be trapped in the transistor channel, leading to performance degradation and leakage issues.
In addition, Micron countered the claim that 4F² outperforms 6F² in density, emphasizing that DRAM bit density is ultimately determined by capacitor pitch (Capacitor
Pitch), not the underlying interconnect pitch.
According to the currently published roadmap, Micron will continue to utilize 6F²-based planar architectures in its upcoming generations of DRAM nodes (expected to persist until 2030), while simultaneously developing 3D DRAM technology.
The HBM roadmap has been significantly expanded, with customization and vertical stacking as key focus areas.
In the highly anticipated HBM sector, Micron has stated that HBM4 is now in mass production, with ramp-up progressing smoothly, and the next-generation HBM4E is already on the roadmap; the company is currently sampling HBM4E to key customers this year.
Looking ahead, Micron expects standard HBM and custom HBM to coexist long-term. Custom HBM integrates memory IP with logic IP onto the base die
In Die), it enables deeper customer co-design. Micron's team noted that future JEDEC standards
Both HBM and custom HBM products will utilize foundry nodes, with HBM4E requiring a more advanced CMOS process due to higher demands for speed, power efficiency, and functionality.
In addition to standard and custom HBM, Micron also emphasizes vertical HBM (Vertical
Two important long-term memory architectures are High Bandwidth Memory (HBM) and vertical Edge Inference Memory (vEIM). Vertical HBM significantly increases bandwidth by placing memory directly above the processor, shortening the path between storage and computation; vEIM employs a similar approach but is specifically optimized for low-power edge AI inference use cases (i.e., vertical HBM emphasizes high bandwidth, while vEIM emphasizes low power consumption).
Micron emphasizes that hybrid bonding, higher stacking layers, advanced thermal management, and co-design with customers are becoming increasingly critical in the HBM roadmap. However, as HBM, vertical HBM, and vEIM advance, these products require more wafers compared to standard DRAM output, meaning the wafer-per-bit conversion ratio will continue to face pressure.
NAND upgrades to G11 across generations, expanding market opportunities with AI-grade products
In the NAND space, Micron, after successfully transitioning through three consecutive leading nodes from G7 to G9, will leap directly to the G11 node, optimized for AI workloads. Compared to G9, G11 aims to achieve approximately 2x higher bit density, up to 1.5x faster I/O speeds, and more than 25% lower energy per bit transferred, with stacking layers exceeding 400.
The G11 node also marks Micron’s formal adoption of wafer-on-wafer bonding technology in NAND manufacturing. The company expects G11 to reach volume production in the second half of 2027 and plans to disclose further details next year. Additionally, Micron intends to continue scaling beyond G11 through new materials and higher-density cell architectures.
At the product level, Micron is developing two AI-grade NAND products: one based on a high-speed SLC design (offering 25 million to 100 million IOPS), specifically engineered to enable GPUs to extract vast volumes of small data blocks for tasks such as vector search and AI context retrieval; and another that stacks NAND dies on top of a logic chip using TSV technology, positioning model weights, long contexts, and KV caches closer to the accelerator—though not directly beside the GPU, as Micron believes this offers no meaningful benefit. Due to higher costs, Micron is co-developing the second product with its customers, and the market share for both products is expected to vary depending on the end-market.
In the data center SSD market, Micron is the first to begin mass production of PCIe Gen6.
The manufacturer that ships SSDs with 245TB drives stands to benefit from lower cost per bit enabled by advanced nodes, supporting further growth in high-capacity drives. J.P. Morgan believes Micron’s NAND roadmap positions it to fully capitalize on AI-driven storage demand growth and maintain or expand its position among the top three global enterprise SSD (eSSD) market share holders.
Deepen customer collaboration and long-cycle R&D; AI tools significantly enhance efficiency.
Micron has detailed a significant shift in its customer collaboration model. Compared to three to four years ago, current collaborations now begin at the concept stage and span joint design, certification, and mass production, including customized projects with multiple cloud service providers (CSPs). For example, Micron is customizing LPDDR6 for Meta (META.US) for data center deployments; and Weka is working with Micron
Ventures' portfolio companies evolved into business partners.
In terms of research and development, Micron’s long-term investments span three time horizons: first, a commitment to invest $550 million in Micron Ventures over 3 to 10 years; second, a partnership with Albany over 5 to 10 years
NanoTech/NY
CREATES is collaborating on the development of a high-NA EUV and lithography roadmap for DRAM; third, the $10 billion Micron Research Lab, announced in the summer quarter, focuses on a 10-year-plus horizon.
In addition, Micron is fully deploying AI technologies across its entire development cycle, from early research to fabrication. Data shows that on its latest data center SSD controller, AI-assisted chip design and verification have halved the time to tapeout compared to the previous generation; AI-generated firmware, root cause analysis, and intelligent test selection have shortened the path to customer-ready silicon for data center SSDs by 60%.
Micron aims to accelerate its path from innovation to high-volume manufacturing (HVM) by two times and is deepening collaborations with suppliers in areas such as lithography, packaging/hybrid bonding, and thin-film processing. JPMorgan believes these efforts are critical to Micron’s ability to advance multiple projects in parallel.