Japan approves TSMC's Kumamoto plant for 3nm production, expected to begin in 2028

Huo Xing Cai Jing reports, according to the Business Times, Japan’s Ministry of Economy, Trade and Industry (METI) has approved the first phase of TSMC’s second factory in Kumamoto Prefecture to produce 3-nanometer advanced semiconductors—marking the first time a Japanese manufacturer will produce 3-nanometer chips. TSMC may further expand capacity with additional support from the Japanese government. Kumamoto Governor Kei Kimura stated that this initiative will spur a new wave of innovative revitalization. The Nikkei newspaper noted that METI has designated TSMC’s Kumamoto II plant as a subsidy recipient; the facility is planned to produce 3-nanometer chips, with commercial production expected to begin in December 2028, and final capacity dependent on the subsidy amount. METI will include the required budget for subsidies in its fiscal year 2027 preliminary budget request; the Japanese government originally planned to provide ¥732 billion in subsidies. Asahi Shimbun reported that the Kumamoto II plant is still under construction and located adjacent to the already-operational Kumamoto I plant. Previously, TSMC planned for the second factory to produce 6-nanometer and 12-nanometer processes with a monthly capacity of 48,000 wafers, including 40-nanometer production; in February, the plan was revised to focus on 3-nanometer production with a reduced monthly capacity of 6,000 wafers. METI has also approved the revised plan for the Kumamoto I plant: originally scheduled for 55,000 wafers per month covering 22–28 nanometers and 12–16 nanometers, the new plan discontinues 12–16 nanometer production and shifts to 45,000 wafers per month of 22–28 nanometer processes.