IT Home, October 23 — During an interview with the Dwarkesh Podcast, Intel’s Chief Technology Officer (CTO) Pushkar Ranade stated that even with sufficient funding, global advanced wafer production is unlikely to expand tenfold; a more realistic upper limit for growth is approximately double.
On the podcast, Ranade was asked whether there are enough tools in the world to increase cutting-edge wafer production tenfold. He responded, “Not tenfold, but perhaps twofold—yes.” He believes this limitation stems from the semiconductor supply chain’s collective ability to scale up, rather than any single环节.
IT Home, citing a blog post, noted that Ranade pointed out that AI computing power has grown at an approximate annual rate of threefold over the past decade, but the key equipment, cleanrooms, and fab scales required to manufacture advanced chips are becoming new capacity ceilings.
ASML produces fewer than 100 EUV lithography machines per year, and it will be difficult to significantly increase production by the end of this decade, while Intel, TSMC, SK Hynix, and other memory manufacturers compete for these devices.
He further explained that equipment ordered today typically takes about 18 months to be delivered, meaning production capacity won’t be realized until around 2028. Building new wafer fabs also cannot automatically increase wafer output, as a key constraint is the insufficient supply of equipment.
Ranard explained that to increase overall production, equipment suppliers, their upstream suppliers, and even deeper-tier sub-suppliers must all simultaneously expand capacity. In other words, as long as any single link—such as lithography machines, critical components, materials, inspection equipment, or factory construction—is a bottleneck, the final output of advanced wafers will struggle to rise significantly.