Unprecedented bandwidth demands require rethinking the optical interconnect roadmap to bring optics closer to silicon chips.
The explosive growth of cloud computing and AI—from generative and inferential models to ultimately intelligent agent systems—is driving unprecedented bandwidth demands, as the volume of data that must be transmitted within and between data centers continues to surge. At the same time, this exposes limitations in the underlying interconnects, which span not only data center networks and rack-level connections but also extend deep into servers, reaching the package and chip levels to connect XPUs, memory, and other system components.
For decades, copper-based electrical interconnects have been the industry standard due to their low cost, simplicity, and reliability. However, they are now approaching fundamental limits: while energy-efficient electrical connections can be achieved, they are typically only viable over very short distances (on the order of millimeters). At longer distances and higher channel rates, power consumption rises sharply, thermal constraints intensify, and signal integrity degrades. In other words, electrical I/O is rapidly becoming a key bottleneck for scaling the next generation of AI and machine learning systems.
Optical interconnects have become a critical path forward. By transmitting data using light instead of electrical signals, optical interconnects are far less sensitive to distance, enabling significantly improved energy efficiency while alleviating the inherent crosstalk and thermal issues of copper interconnects. However, even optical technologies are now being pushed to new limits, as the industry demands (multi-)terabit-per-second interfaces, ultra-high energy efficiency, and extremely low (sub-microsecond) latency.
Meeting these requirements cannot be achieved through incremental innovation alone. It requires a fundamental rethinking of the optical interconnect roadmap—gradually moving optics from the front panel into the package, and ultimately integrating them firmly into the wafer stack.
Pluggable Optical Module (PO): A long-standing and still actively used primary solution
For over two decades, pluggable optical transceivers have been a cornerstone of high-speed telecommunications and data communication networks—essential for enterprise workloads, video streaming, and today’s hyperscale cloud infrastructure. These pluggable modules insert into standardized ports on switches, routers, and servers, converting electrical signals from the host into optical signals for fiber transmission, and vice versa at the receiving end.
The advantages they bring include:
- Modularity and flexibility—the optical component can be upgraded independently of the electrical host.
- Maintainability—Plug-in modules support hot-swapping, allowing replacement without system downtime.
- Multi-vendor interoperability—achieved through the IEEE 802.3 standard and widely adopted multi-source agreement (MSA) form factors such as QSFP, QSFP-DD, and OSFP.
- Thermal stability—The optical engine is located in a front-panel slot, physically isolated from high-power ASICs; this helps protect the laser, modulator, and photodetector from overheating, enhancing reliability.
Over successive generations of products, pluggable optical transceivers have scaled from 100/200G to 400G and 800G by increasing the baud rate (symbols per second per optical channel), adopting higher-order modulation (such as PAM-4), and increasing the number of parallel channels.
Although the technology is relatively mature, pluggable optical modules continue to evolve. For example, the first-generation 1.6T pluggable transceivers—relying on a data rate of 200 Gbps per channel and employing an eight-channel parallel architecture—are nearing the sampling and early deployment stages, with target applications including direct-connect (DR) links within data centers and forward-reach (FR) connections over single-mode fiber.
The key enabler is silicon photonics (SiPho), which supports this scaling through a series of silicon-based optical and electronic components, including Mach-Zehnder modulators. These devices enable 200 Gbps per channel operation at a cost-effective price while keeping power consumption under control.
Looking further into the future, by the end of this decade, the industry is targeting the milestone of 3.2T pluggable optical modules. However, achieving these performance levels requires continued advancements in high-speed electronics, packaging, and thermal management, as well as a significant expansion of the silicon photonics toolbox. For example, on the transmitter side, optical modulators will need to support bandwidths exceeding 100 GHz while maintaining low insertion loss and high modulation efficiency—requirements that are increasingly difficult to meet with traditional silicon devices alone.
Figure 1: Over the past several years, pluggable optical modules have achieved order-of-magnitude improvements in bandwidth density and energy efficiency. Source: imec.
In response to these limitations, the industry is increasingly focusing on heterogeneous integration of higher-performance electro-optic materials, such as lithium niobate (LiNbO₃) and lithium tantalate (LiTaO₃). Techniques like micro-transfer printing offer promising pathways for integrating these materials onto silicon photonic platforms. Early results are encouraging, but further research is needed to scale these methods for mass production, ensuring that future 3.2T modules remain practical, reliable, and cost-competitive—upholding the cost discipline that has made pluggable optical modules the industry standard.
Meanwhile, other expansion pathways are also being explored. Concepts such as the Extreme Pluggable Optical module (XPO) aim to increase capacity to 12.8T by further boosting bandwidth density, but at the cost of significantly increased system complexity and the need for liquid cooling, which currently impacts cost and practical deployment.
Dual world first: Integration of LiNbO₃ and LiTaO₃ onto SiPho via micro-transfer printing
As optical interconnects push beyond the current standard of 200 Gbps per channel, GeSi-based devices are increasingly struggling to deliver the required combination of bandwidth and energy efficiency. Although GeSi modulators have achieved 400 Gbps per channel in the C-band, this level has not yet been reached in the O-band. To enable the next performance leap in pluggable optical interconnects, researchers are exploring the heterogeneous integration of advanced electro-optic materials—such as lithium niobate (LiNbO₃) and lithium tantalate (LiTaO₃)—onto silicon photonics, paving the way for the next generation of high-speed modulators and photodetectors.
A highly promising approach is microtransfer printing, which enables precise placement of thin-film materials onto SiPho wafers without the material waste, post-bonding complexity, and cost typically associated with traditional wafer bonding. Two world-first achievements demonstrate its potential:
First, imec and Ghent University researchers demonstrated a 2-kilometer single-mode fiber, amplifier-free optical link operating at 320 Gbps in the O-band. The achievement utilized a high-bandwidth 100 GHz germanium photodiode combined with a transferred thin-film lithium niobate Mach-Zehnder modulator (MZM), integrated onto a SiPho platform and co-packaged with a custom traveling-wave driver and TIA. This work marks the first seamless integration of a LiNbO₃ modulator onto a silicon photonic platform via micro-transfer printing.
Figure 2: Seamless integration of a LiNbO₃ modulator onto a silicon photonic platform via micro-transfer printing. Source: imec.
The research team also achieved the first successful heterogenous integration of a LiTaO₃ modulator onto a silicon photonic integrated circuit. Using the same micro-transfer printing technique previously employed for lithium niobate, the researchers ensured full compatibility with the entire wafer stack, enabling seamless integration with other photonic components such as heaters, filters, and germanium photodetectors without compromising performance.
Although these modulators are still relatively large, they offer a viable path for further scaling of pluggable transceivers, as such products have less stringent constraints on footprint. Meanwhile, researchers are exploring other device concepts to meet the future demands of co-packaged optics for smaller sizes and higher integration levels. These approaches include compact, ultra-high-speed GeSi modulators operating in the C-band, as well as emerging methods based on integrating III-V materials onto silicon photonic platforms.
Further work is needed to scale these heterogeneous integration approaches to mass manufacturing. However, these results demonstrate that integrating electro-optic devices exceeding 100 GHz onto SiPho is a promising path—capabilities widely regarded as essential for next-generation optical interconnects in future 3.2T pluggable modules and AI-driven infrastructure.
Fast and Narrowband Co-Packaged Optics (CPO): A Key Pillar of the Optical Interconnect Roadmap
At this scale, a new set of constraints emerges. Pluggable optical transceivers rely on extremely high baud rates combined with complex digital signal processing (DSP) to compensate for signal degradation. While this works well at the rack or data center level, the power consumption and latency introduced by heavy DSP become increasingly problematic for short-reach chip-to-chip optical interconnects in AI and machine learning systems. Instead, these scenarios require intrinsically cleaner optical channels with extremely low bit error rates, enabling each channel to operate without relying on excessive equalization or DSP overhead.
This shift is precisely what is driving the adoption of rapid, narrow-band co-packaged optics (CPO). In CPO systems, optical components are placed extremely close to the (switching) silicon or compute chip, reducing electrical pathways from several centimeters in pluggable solutions to just a few millimeters—or even less. By positioning the electro-optical conversion point directly next to the ASIC—within the same package—CPO significantly improves signal integrity, minimizes electrical losses, and reduces latency—all without relying on power-hungry DSPs. This makes CPO an attractive architecture for scaling next-generation AI and high-performance computing systems.
Figure 3: Co-packaged optics shortens the electrical path between the optical engine and the host IC, increasing bandwidth density and eliminating the need for digital signal processing, thereby improving energy efficiency. Source: imec.
However, as early CPO deployments begin to emerge, integration complexity remains one of the core challenges of this technology. Unlike pluggable optical modules, which are largely self-contained, CPO requires tight co-design and joint optimization—including photonic integrated circuits (PICs), electronic ICs (EICs), switching ASICs, fiber coupling strategies, thermal management, and advanced packaging. Addressing this multidisciplinary challenge is one of the core objectives of imec’s optical interconnects program.
In the CPO domain (also known as OIO2.5D), imec’s primary research objectives include:
- Expand the optical engine capacity from 1.6T and 3.2T to 6.4T, ultimately reaching 12.8T.
- Achieve fast and narrow-band 400 Gbps channel rates and increase bandwidth density to nearly 1 Tbps per millimeter.
- Integrate the full optical stack—modulator, photodetector, coupler, fiber connections, and thermal solutions—into a manufacturable package.
Achieving these goals largely depends on advanced semiconductor packaging technologies to enable high-density integration of photonic and electronic components—such as 2.5D interposer architectures, through-silicon vias (TSVs), fan-out wafer-level packaging (FO-WLP), and increasingly, 3D integration enabled by hybrid bonding—alongside the use of advanced (III-V) materials.
There is also the issue of light sources. Although the long-term goal is to directly integrate lasers onto photonic chips, early CPO systems will still rely on external laser sources. This approach simplifies thermal management and alleviates longstanding reliability concerns about operating lasers near high-temperature ASICs. The trade-off is that higher output power, more complex packaging, and additional fibers and connectors are required to deliver light into the package to compensate for optical losses.
Achieve the first silicon-based EAM transmission of 400 Gbps per channel
In October 2025, imec announced a major advancement in next-generation optical interconnects: a C-band, GeSi electro-absorption modulator (EAM) with a bandwidth exceeding 110 GHz, enabling a net data rate of 400 Gbps per channel.
This device leverages the Franz-Keldysh effect, offering a compact size, high speed, and low power consumption. Thanks to its GeSi-based architecture, it can be seamlessly integrated into 300mm CMOS-compatible SiPho platforms, providing a clear pathway for mass production.
This breakthrough reflects over a decade of coordinated progress at both the device and system levels. At the device level, imec has optimized device dimensions, doping schemes, and epitaxial growth processes. At the system level, a robust PAM-4 IM/DD transmission scheme has demonstrated sustained net operation at 400 Gbps per channel, proving that GeSi EAM technology is practically viable for next-generation high-channel-rate optical engines.
3D Integrated Optics (OIO3D): The Next Frontier
As AI and machine learning systems scale to thousands of tightly interconnected accelerators, each connected via high-bandwidth memory stacks and adjacent processors at distances of just a few millimeters, the demands on optical interconnects become increasingly extreme. Over the next decade, these systems are expected to require bandwidth densities approaching and exceeding 10 Tbps per millimeter, energy efficiency well below 1 pJ/bit, and ultra-low latency (<100 ns). These targets exceed the capabilities of even the most advanced CPO architectures.
To meet these requirements, optics must transcend the package and enter the wafer stack itself. This is the foundation of 3D integrated optics. By compressing electrical paths to micrometer-scale distances, OIO3D enables ultra-short, high-bandwidth, and energy-efficient optical links, making high-density inter-chip optical networks possible.
Figure 4: By compressing electrical pathways to micrometer-scale distances, OIO3D enables ultra-short, high-bandwidth, and energy-efficient optical links, making high-density inter-chip optical networks possible. Source: imec.
Achieving 3D integrated photonics requires overcoming several major technical challenges. These include scalable laser integration, the development of high-efficiency and high-bandwidth electro-optic devices (such as those based on GeSi, lithium niobate, lithium tantalate, indium phosphide, or barium titanate), and robust thermal management in high-density stacking environments. Equally critical are wafer-level ultra-precise bonding and alignment technologies.
OIO2.5D and OIO3D
As a step in the evolution of the CPO, OIO2.5D achieves a balance between high-density photonic integration and manageable packaging complexity by placing photonic and electronic chips side by side on a shared silicon interposer. The photonic layer is integrated using die-to-wafer copper-based hybrid bonding, enabling ultra-short, low-parasitic electrical pathways.
This architecture was originally designed for optical engines in the 8–32 Tbps range. It leverages a per-channel rate of 32–64 Gbps, optimized for low-power, DSP-free operation to minimize latency and heat generation. Wavelength division multiplexing (8–32 wavelengths per fiber) further increases total bandwidth without requiring additional fibers. The technology roadmap aims to achieve a bandwidth density of 2 Tbps per millimeter and energy efficiency approaching 2 pJ/bit.
OIO3D represents the most advanced and ambitious vision for optical interconnects, where the photonic layer is stacked directly above or below the computing silicon chip to create a true chip-level optical network, reducing electrical pathways to micrometer-scale distances.
This approach relies on die-to-wafer and wafer-to-wafer hybrid bonding to enable ultra-fine-pitch vertical interconnects. With this level of vertical integration, OIO3D aims to scale bandwidth capacity to tens of terabits per second and beyond, while targeting an energy efficiency of approximately 2 pJ/bit, with a longer-term goal of achieving sub-pJ/bit operation.
A key research direction is wafer-scale laser integration using heterogeneous III-V approaches such as quantum dot GaAs-on-Si. Pilot production lines under the EU’s Chips Act are actively exploring this direction to serve future large-scale photonic systems.
Integrate barium titanate on the 300mm SiPho platform
In January 2026, Veeco Instruments Inc. and imec announced a process suitable for 300mm mass manufacturing that integrates barium titanate (BaTiO₃, BTO) onto silicon photonic platforms.
BTO exhibits exceptional electro-optic properties, making it suitable for high-speed, low-power modulators in applications ranging from optical transceivers to quantum photonics, LiDAR, and AR/VR. However, historically, large-scale integration of BTO onto silicon platforms has been challenging due to cost, uniformity, and manufacturability constraints.
Through its collaboration with imec, Veeco has recently delivered its first molecular beam epitaxy (MBE) cluster system designed for 300mm wafers. This platform enables the growth of single-crystal BTO films on silicon using solid-state and hybrid MBE processes, offering improved repeatability, material quality, and total cost of ownership compared to traditional MBE solutions.
Timeline Overview
Looking across the development of interconnectivity, it is clear that different paths are advancing along different timelines.
Pluggable optical modules have been widely deployed globally and are now entering a phase dominated by incremental technological improvements rather than fundamental breakthroughs. The roadmap continues—progressing toward 1.6T and 3.2T modules—and even as new architectures scale up, pluggable solutions will remain competitive in many use cases.
Co-packaged optics is also approaching a relatively mature stage. Key components are transitioning to pilot production lines, supply chain preparation, and wafer-level services—although the industry continues to pursue higher bandwidth, faster channel rates, and better energy efficiency. Large-scale CPO deployment is expected to begin around 2027/2028.
3D integrated photonics is still in an early stage of research and development. Current efforts are focused on pathway exploration and building device/integration toolkits. The first proof-of-concept demonstrators are expected to emerge within three to five years, with broader commercialization anticipated within five to ten years.
Bring the next-generation optical interconnects to market
Through its optical interconnect research project, imec is developing key components for future optical transceivers, anticipating market demand years in advance.
imec’s advantage lies in its truly integrated R&D environment, bringing together expertise in silicon photonics, advanced CMOS, 3D integration, materials research, and system-level modeling. This breadth enables researchers to explore new concepts faster than in a large-scale manufacturing environment, resulting in shorter development cycles and the freedom to experiment with unconventional integration approaches. The project also benefits from imec’s Cross-Technology Co-Optimization (XTCO) strategy, which drives scaling across technology domains.
A key accelerator is the close collaboration between imec’s photonic interconnect research team and IC-Link—imec’s semiconductor manufacturing pillar. imec’s early-stage research focuses on path exploration and prototype development, while IC-Link helps advance the technology to higher technology readiness levels by optimizing manufacturing processes, enhancing manufacturability, establishing test strategies, and engaging the broader supply chain. Through IC-Link, industry partners can also access and evaluate these technologies using imec’s 200mm and 300mm iSiPP silicon photonics platforms, paving the way from early innovation to industrial deployment.
In addition to IC-Link, imec maintains close collaboration with industry partners through various cooperation models, including guided projects (where imec and partners jointly explore emerging technologies), targeted bilateral projects tailored to specific partner needs, and long-term core partnership relationships. Meanwhile, imec also works closely with equipment suppliers to enable early validation of advanced tools and process capabilities before commercialization.
These collaborations ensure that imec’s optical interconnect research remains grounded in real-world system requirements while accelerating the transition of advanced technologies into market-ready solutions.
Peter Ossieur earned his Master’s degree in Electrical Engineering from Ghent University, Belgium, in 2000, and his Ph.D. in Electrical Engineering from the same institution in 2005. From 2005 to 2009, he served as a postdoctoral researcher at Ghent University before joining the Tyndall National Institute, where he advanced to Senior Researcher. His research interests include electronic integrated circuit design and optical transmission systems. In 2017, he joined imec-IDlab within Ghent University. Today, he is the Director of imec XTCO Fabric and Optical Interconnect and holds an adjunct professor position at Ghent University. Peter Ossieur is also a member of the ISSCC Wired Communications Technical Committee.
Imene Jadli