Huawei's "Tao's Law" V2 Paper Released, Kirin 2026 Data Revealed

ME News report: On July 4 (UTC+8), according to monitoring by Beating, He Tingbo, head of Huawei’s semiconductor division, published the Version 2 paper of “Time Microscaling Theory for Multi-Level Electronic Systems” (Tao’s Law) on ChinaXiv, the Chinese Academy of Sciences’ preprint platform for scientific papers, on July 3. Compared to the Version 1 paper released on May 25, the new version adds extensive engineering implementation details and empirical quantitative data, forming a complete eight-chapter framework. It also introduces new diagrams explaining the principles and physical implementations of core technologies including the τ-layered spatiotemporal model, LogicFolding architecture, bonding interface cross-sections, Unified Bus interconnect architecture, and the Hi-ONE optical engine. In terms of engineering implementation, Version 2 thoroughly explains the concept of “gear ratio” in LogicFolding: when hybrid bonding pitch approaches the dimensions of top-level metal routing, the 3D design space shifts from traditional “macro-block discrete optimization” to “unit-level continuous optimization,” enabling globally optimal vertical logic partitioning and overcoming the limitation of conventional 3D stacking, which can only layer by functional blocks. Version 2 also presents, for the first time, real-world production measurement data tables, explicitly listing voltage, frequency, normalized power consumption, area, and power density parameters for the Kirin 2026 and the baseline Kirin 9030 Pro, further validating the post-Moore scaling theory centered on the time constant τ through empirical evidence. --------------------------------- Click the link below to join Beating’s Feishu AI News Channel for 24/7 real-time monitoring of global AI trends and news. (Source: BlockBeats)