High-NA EUV market splits as Intel leads, TSMC waits, and Samsung hesitates

Today, High-NA EUV has crossed the threshold of technical validation, but the three major foundries have clearly diverged in their approaches: Intel is pushing ahead, TSMC is doing the math, and Samsung is hitting the brakes. At this point, the difference among their strategies isn’t about who advances first, but who needs High-NA the most.

In July 2026, ASML announced that Intel has begun high-volume manufacturing using EXE-series High-NA EUV tools on specific Intel 18A process layers in certain Panther Lake products. The relevant High-NA process layers have achieved yields comparable to those of traditional NXE low-NA EUV platforms.

However, not the entire Intel 18A process uses High-NA, nor do all Panther Lake products use High-NA—only certain products and specific critical layers do. In other words, Intel is not replacing Low-NA with High-NA across the board, but rather validating exposure, overlay, equipment utilization, yield, and maintenance data in real-world production environments.

Back in 2024, Intel and ASML completed the integration of the world’s first commercial high-NA EUV lithography system at their research and development center in Hillsboro, Oregon. Intel Foundry was also the first company to install and pass the acceptance test for the second-generation TWINSCAN EXE:5200B. The TWINSCAN EXE:5200B, based on the TWINSCAN EXE:5000, features an improved light source while enhancing output power and overlay accuracy.

Why is Intel the most aggressive? Because for Intel, the value of High-NA isn't just about reducing multiple patterning steps—it's about establishing a differentiated advantage for Intel 14A.

This is a pivotal moment for Intel Foundry. Recently, Intel Foundry secured orders from AMD, NVIDIA, and OpenAI, with its 18A and 14A process node designs winning bids. According to WccfTech, the yield for the 18A process has increased from 65% last quarter to 85%, just below TSMC’s N2 (2nm) process at 90%, but significantly higher than Samsung’s SF2 process, which has a yield of 50–60%.

High-NA is another powerful advantage for Intel. Intel’s official roadmap has designated High-NA EUV as a key technology for Intel 14A, alongside PowerDirect backside power delivery. If Intel can achieve early mass production of High-NA, it will not only have the opportunity to improve transistor density and reduce process complexity but also demonstrate to potential foundry customers that it remains capable of leading the adoption of the next-generation manufacturing platform.

Thus, Intel’s strategy can be summarized as: first, use High-NA in a limited number of production layers at 18A to gain experience, then expand its use at 14A. This path is the most costly and carries the highest risk, but Intel must leverage technological leadership to buy time. For TSMC, High-NA is a cost decision; for Intel, it is more like a necessary demonstration of process superiority.

TSMC has adopted a more cautious stance toward High-NA. With over 90% of the global market share in advanced process manufacturing, TSMC serves major clients such as Apple and NVIDIA. Its top priority is helping customers control costs, maintain high yields, and ensure stable deliveries. Therefore, for nodes ranging from 2nm (N2) to A16 and A14, TSMC has clearly stated that it does not rely on High-NA EUV.

At the Q2 2026 earnings call, TSMC CEO C.C. Wei explicitly acknowledged that High-NA is a high-performance tool, but emphasized that its adoption timeline depends on three factors: technical capability, maturity, and cost合理性. Wei also specifically highlighted the partial field issue with High-NA equipment. Due to its use of anamorphic optics, the exposure area per shot is only half that of conventional EUV, meaning larger chips may require field stitching, which introduces challenges in overlay, yield, production efficiency, and design constraints. TSMC will account for all these factors in its manufacturing costs.

TSMC's confidence in not needing High-NA for the A14 stems from the fact that the A14 does not rely on High-NA. Without High-NA, how did TSMC achieve a 20% density improvement for the A14?

TSMC has distributed the resolution benefits originally provided by High-NA EUV across multiple areas—including transistors, standard cells, masks, computational lithography, patterning, interconnects, and yield control—continuing to extend 0.33 NA EUV through a comprehensive set of collaborative optimizations. TSMC currently plans to begin risk production of A14 in 2027 and mass production in 2028.

Specifically, A14's primary gains come from the transistors themselves, which utilize its second-generation nanosheet GAA transistor architecture. Compared to N2, A14's latest publicly stated targets are: a 10%–15% performance improvement at the same power consumption, or a 25%–30% reduction in power consumption at the same performance level, along with nearly a 20% increase in logic density.

Another publicly disclosed core technology of A14 is NanoFlex Pro. Through design-technology co-optimization (DTCO), it enables customers to make more granular choices among performance, power, and area based on different functional modules. Senior Vice President Kevin Zhang of TSMC has explicitly stated that A14 significantly delays reliance on high-NA lithography machines through robust design-technology co-optimization (DTCO).

Another is Low-NA multiple patterning. The A14 will continue to use 0.33 NA EUV as its primary advanced lithography platform, maintaining single exposure on layers that can be printed in one step, and only adding necessary pattern splitting and multiple patterning on the few most critical, tightly spaced, and complex layers.

Mask technology is also a critical factor. TSMC is enhancing the manufacturability of 0.33 NA EUV for extreme patterns through more complex curved masks, higher-resolution multi-electron-beam writing, and finer mask correction. In its annual report, TSMC explicitly disclosed that its mask technology development for the A14 node and beyond includes: optimizing EUV mask substrate materials, improving the resolution of multi-electron-beam mask writers, refining mask fabrication processes, enhancing critical dimension uniformity of curved patterns, improving pattern fidelity and overlay accuracy, and employing advanced electron-beam inspection and repair technologies to reduce mask defects. TSMC is also developing new EUV mask protective films and mask substrates to improve yield, productivity, and equipment utilization efficiency.

TSMC’s greatest advantage is precisely its ability to wait. It has the largest installed base of NXE tools, mature multi-patterning technology, higher capacity utilization, and stable customer demand, eliminating the need to prematurely bear the depreciation of High-NA equipment to prove technological leadership.

This does not mean TSMC is rejecting High-NA. TSMC has already initiated the development of lithography technologies for High-NA scanners in 2025, but it prefers to wait until the following conditions are met: improved throughput and availability of High-NA tools; maturation of the ecosystem for resists, masks, inspection, and metrology; cost savings from using High-NA exceeding additional depreciation; sufficient customer orders to amortize equipment costs; and control over large-chip half-field stitching issues.

According to the latest reports from TrendForce and the Korean industry, Samsung has completed the installation of two ASML High-NA EUV systems (including the Twinscan EXE series) at its Hwaseong campus, with total investment exceeding 1 trillion Korean won (approximately $770 million). The first system was installed in 2025 for research and development testing, and the second was introduced in the first half of 2026. However, Samsung has not yet officially integrated these systems into any commercial production lines, and overall mass production deployment remains on hold and under review.

The report analysis suggests that Samsung’s caution stems not from technological shortcomings, but from severe profitability pressures on its foundry business. High-NA equipment costs approximately $400 million per unit—nearly double the price of traditional Low-NA EUV systems. At this sensitive juncture, with the foundry division under sustained pressure since 2022 and striving to break even, immediately deploying this equipment on commercial production lines would immediately burden the financial statements with massive depreciation, facility operations, exclusive photomask, and associated R&D costs, easily dragging the foundry business back into losses.

Samsung faces several practical challenges: First, the number of client agreements and order volumes for advanced nodes (such as 2nm GAA) still lag behind TSMC; if utilization rates are insufficient to amortize depreciation, costs will become unsustainable. Second, although reports indicate Samsung has made significant progress in 2nm pilot production yields, High-NA equipment alone cannot automatically resolve transistor architecture optimization at the nanometer scale, EDA software ecosystem development, or packaging support. Third, under pressure from Intel’s high-profile adoption of High-NA for its 18A/14A nodes and TSMC’s cautious wait-and-see approach, Samsung risks significantly increasing its fixed-cost exposure if it proceeds with large-scale mass production prematurely.

Therefore, Samsung’s more rational current strategy is “prepare but do not use”: keeping the procured High-NA equipment in R&D and pilot lines for trial production and process exploration, while strictly controlling commercial-scale expansion.

In the future, Samsung’s most likely breakthroughs will remain in the 1.4nm (SF1.4) logic process and next-generation vertical channel transistor (VCT) advanced DRAM. Particularly in DRAM, as memory cell pattern resolution falls below 10nm and approaches physical limits, the number of mask layers and process complexity with Low-NA multi-patterning are sharply increasing. The economic value of High-NA EUV, which simplifies the process through single-exposure, may emerge sooner than in logic foundry. However, Samsung has not yet officially announced a clear timeline for mass production.

Unlike logic foundries like TSMC and Samsung, which have been hesitant due to partial field-of-view and massive costs, storage leader SK Hynix has taken a highly decisive approach to High-NA EUV.

In September 2025, SK Hynisi installed the industry’s first production-ready High-NA EUV lithography system at its Hwaseong M16 facility. Unlike Intel’s earlier pilot-scale EXE:5000, SK Hynisi deployed ASML’s TWINSCAN EXE:5200B—a model specifically designed for high-volume, mass production with a wafer throughput of over 175 wafers per hour.

SK Hynix plans to gradually integrate High-NA into the most advanced 0a nm-class DRAM production around 2026–2027, and potentially into future 3D DRAM (vertical-structure DRAM).

For logic foundry companies like TSMC, large chips (such as AI GPUs) face the "half-field" cutting and tiling challenge with High-NA, resulting in reduced exposure efficiency. However, the physical characteristics of memory chips (DRAM) are entirely different:

1) Avoid the nightmare of multiple patterning: As DRAM technology scales to the 1b, 1c, and even 0a nodes (below 10nm), continuing to use Low-NA EUV would require three or even four EUV multiple patterning steps. This leads to a dramatic increase in mask layers and an extremely complex process flow, resulting in significantly reduced yields. High-NA single-exposure technology can greatly simplify the manufacturing process.

2) Supporting HBM's core scaling requirements: The technological evolution of HBM imposes nearly stringent demands on the capacitance density and channel linewidth of underlying DRAM chips. To maintain its absolute dominance in NVIDIA’s supply chain, SK hynix must rely on High-NA to achieve higher integration and extreme performance at smaller dimensions.

No matter what strategies the foundries employ, ASML, as the sole supplier, remains unbeatable.

For example, in its second-quarter 2026 financial results: ASML achieved net sales of €9.3 billion, a gross margin of 54.0%, and a net profit of €2.9 billion. Of the €6.6 billion in system sales, EUV equipment revenue amounted to approximately €3.8 billion, while non-EUV equipment revenue was approximately €2.8 billion; the EUV revenue includes only one High-NA system.

In other words, although High-NA has significant strategic value and a high unit price, it is not currently the primary driver of ASML's revenue growth.

ASML's true "three-horse team" is powering ahead:

The first is Low-NA EUV.

ASML expects to deliver approximately 65 Low-NA EUV systems in 2026 and plans to increase Low-NA EUV capacity by another 30% in 2027, while already securing a significant number of orders for 2028. The reason is straightforward: 2nm, 3nm, HBM, advanced DRAM, and subsequent nodes still require substantial volumes of 0.33 NA EUV tools. Even as some critical layers transition to High-NA, many other process layers will continue to use the NXE platform.

The second is DUV immersion equipment.

ASML plans to increase the production capacity of its DUV immersion tools by approximately 30% by 2027, from the current capacity of about 130 units, and is researching a further 30% capacity increase by 2028. This is because not all layers in advanced chips require EUV; a significant number of non-critical layers, mature processes, analog chips, power devices, and advanced packaging still rely on DUV. The emergence of High-NA EUV will not eliminate demand for DUV; rather, DUV demand may grow in tandem with overall fab capacity expansion.

Third, many people might not think of it: installation and upgrade services.

In the second quarter, ASML's installed base revenue approached €2.8 billion. As the global installed base of EUV and DUV systems grows, ongoing revenue is generated from maintenance, upgrades, source power enhancements, productivity improvements, and computational lithography services. This revenue stream exists regardless of whether customers choose to adopt High-NA early or continue relying on Low-NA multi-patterning.

ASML currently expects total net sales for 2026 to be between €43 billion and €45 billion, with a gross margin between 54% and 56%.

Regardless, competition in High-NA EUV has moved from technical feasibility to economic feasibility.

ASML's High-NA offers an 8-nanometer resolution, enabling the printing of features approximately 1.7 times smaller than those achievable with 0.33 NA EUV, with a theoretical potential to increase transistor density by about 2.9 times and possibly replace some multi-patterning steps with single-exposure lithography. However, whether it is more cost-effective than Low-NA depends on factors such as equipment cost, partial-field exposure, chip stitching, resist, masks, inspection equipment, throughput, and utilization rate.

The ultimate divergence among the four giants reflects their respective business realities: Intel lacks time, so it’s willing to pay a premium for technological leadership; Samsung lacks foundry profits, so it dares not blindly expand fixed depreciation; TSMC doesn’t lack technology, so it calmly calculates the optimal ROI; SK Hynix, seeking an absolute barrier in HBM, took an early lead in the memory segment; and ASML, having secured nearly all global orders, emerged as the biggest winner behind this strategic divergence.

This article is from the WeChat public account "Semiconductor Industry Watch" (ID: icbank), authored by Du Qin (DQ).