CXMT to List on the Sci-Tech Innovation Board, Expected Revenue of 50 Billion in 2026

Authors: Ray Wang, Myron Xie, Dylan Patel, et al.

Compiled by: DeepWave TechFlow

DeepInsight Summary: ChangXin Memory Technologies (CXMT) is set to list on the STAR Market, potentially becoming the largest semiconductor IPO in Chinese history. Founded in 2016, the company began by acquiring patents and talent from the bankrupt German DRAM manufacturer Qimonda, and, with nearly a decade of capital support from the Hefei government despite persistent losses, achieved its first profit in 2025 and recorded quarterly revenue of $7.3 billion in the first quarter of 2026. This 10,000-word report by SemiAnalysis breaks down ChangXin’s technical roadmap, financial data, HBM challenges, and IPO structure — essential reading for understanding China’s position in the memory chip industry.

The SemiAnalysis team was among the first to highlight in their newsletter at the end of 2024 the massive memory demands of AI inference and agent workflows, subsequently releasing multiple in-depth reports on memory and continuously tracking CXMT and China’s computing ecosystem. With CXMT set to go public in the coming months, a dedicated in-depth research report is essential. CXMT is likely to become China’s largest semiconductor IPO and a landmark milestone for this leading Chinese memory manufacturer. From here on, competition between CXMT and Samsung, SK Hynix, and Micron will only intensify.

The founder of CXMT, Zhu Yiming, graduated with a bachelor’s degree in physics from Tsinghua University in 1994 and later pursued electrical engineering at Stony Brook University, State University of New York. He worked in Silicon Valley for many years and became a project lead at MoSys (Monolithic System Technology) around 2001. In 2005, Zhu Yiming returned to China with a set of SRAM patents and $100,000 in seed funding to found GigaDevice, which later became one of the world’s leading NOR Flash suppliers. However, the global NOR Flash market is much smaller than that of DRAM or NAND Flash. Zhu Yiming had bigger ambitions and chose to enter the DRAM sector.

DRAM is not a game for fabless companies. DRAM consumes massive capital, has stringent patent barriers, and is highly dependent on manufacturing capabilities. By 2016, the entire industry had been reduced to only three survivors: Samsung, SK Hynix, and Micron—whose decades-long accumulation of patents and capital created an insurmountable moat that no new entrant could breach. Zhu Yiming’s SRAM patents and GigaDevice’s NOR Flash business could neither provide DRAM memory cell design nor DRAM manufacturing processes, nor could they circumvent the patent blockades of the giants. Therefore, when Zhu Yiming and the Hefei municipal government launched the DRAM project “Project 506” (later known as CXMT) in 2016, the core technologies had to be acquired externally.

The source is a defunct German company.

The defunct company was Qimonda. Qimonda went bankrupt in January 2009 due to the global financial crisis and the subsequent collapse in memory prices, but at the time it was one of Europe’s leading DRAM manufacturers. As a subsidiary of Infineon, tracing its roots back to Siemens, Qimonda offered a rare alternative: a deep portfolio of DRAM patents and a memory cell architecture outside the Samsung-Hynix-Micron triangle.

In June 2015, Polaris Innovations, a subsidiary of the Canadian patent operating company WiLAN, acquired approximately 7,000 Qimonda patents and applications from Infineon for around €30 million. In December 2019, Polaris signed an agreement with CXMT, licensing a large portfolio of DRAM patents. CXMT executives have publicly stated that they received approximately 2.8 TB of Qimonda technical documentation, which became the foundation of CXMT’s DRAM business.

One key technology inherited and advanced by CXMT from Qimonda is the 46nm-class Buried Wordline (BWL) memory cell, and has pushed it toward the 10nm node. BWL is a core architectural innovation: while traditional designs route the access transistor’s gate along the wafer surface, BWL embeds the gate into a trench beneath the bit line. This offers three advantages: shrinking the memory cell to a 6F² layout (compared to 8F² traditionally), extending the channel length without consuming surface area to suppress short-channel leakage (which affects data retention), and reducing gate-to-bit-line parasitic capacitance. The combination of buried wordline and stacked capacitor is the architecture now used by all three major memory manufacturers. Qimonda, which had steadfastly pursued the trench approach, retained the technical expertise in stacked/BWL designs—exactly what CXMT acquired.

Beyond patents, the more enduring asset XMC gained from the collapse of Qimonda was its engineers. Qimonda operated a research and development center in Xi’an with 400–500 engineers, one of its largest R&D hubs outside Germany. After Qimonda’s bankruptcy, although the entire Xi’an R&D center was acquired by Tsinghua Unigroup, the broader dispersion of talent benefited XMC.

ChangXin also successfully attracted senior engineer Karl-Heinz Kuesters from Qimonda’s headquarters in Germany. Kuesters served as Vice President of Technology and Pre-Research at Siemens, Infineon, and Qimonda for 24 years. The pre-research production line he led was precisely the stacked capacitor architecture that ChangXin ultimately adopted. Joining ChangXin as a technical advisor, EE Times called Kuesters ChangXin’s “secret weapon.” What Kuesters brought could not be captured by patents or 2.8 TB of documentation—it was tacit know-how: two decades of experience in DRAM development enabled him to guide ChangXin’s engineers on which Qimonda designs to retain, which to discard, and how to transition memory cells proven in the lab into mass production. This kind of integration and yield judgment does not exist in any patent literature.

The U.S. side follows the same pattern. Ping Er-xuan, the vice president responsible for future technology evaluation at CXMT—who publicly outlined the "46nm to 10nm" roadmap—did not come from Qimonda, but instead has an extensive U.S. career at Micron, SanDisk, and Applied Materials, with deep expertise in memory and materials technology.

ChangXin has also extensively recruited talent from South Korea and Taiwan. South Korean prosecutors have previously prosecuted former Samsung employees for leaking technology, and it is reported that dozens of South Korean engineers have worked at ChangXin. A similar situation exists in Taiwan, where ChangXin has consistently poached top equipment and process engineers with generous salaries.

This is the key to understanding Hynix’s trajectory. Qimonda’s patents were always limited, expiring assets. What enabled Hynix to advance from G4 to G5 and then to HBM was not documentation, but the aggregated talent—locally trained professionals, Chinese engineers who returned after working at foreign companies, and a small number of foreign experts. The legacy was merely a starting point; talent transformed this foreign inheritance into a self-driven engine. But it took nearly a decade for this engine to become profitable. The question is, who has the patience to sustain this funding?

XMC's success is hard to attribute to anything other than strong support from China's local and central governments. The Hefei municipal government is a classic example. Hefei is a major hub for technological innovation in China and has, over the past two decades, nurtured a string of successful companies through its model of "patient state-owned venture capital": BOE (a global leader in display panels), NIO (a leading electric vehicle manufacturer), and now XMC Storage.

The Hefei municipal government did two key things for ChangXin.

First, help ChangXin build a local supply chain around its factory. Hefei’s strategy is to take substantial equity stakes in core “chain leader” enterprises, then attract the rest of the industry chain. This approach was used in the display panel sector with BOE, in the electric vehicle sector with NIO, and since 2016, the same playbook has been replicated with ChangXin. Around ChangXin’s factory in Hefei’s Air Port Economic Zone, the government has cultivated a dense local industrial cluster. Packaging and testing firms Peidun and Xinfeng are located just one wall away from ChangXin’s facility, with Xinfeng generating over 99% of its revenue from ChangXin. Guanggang operates an on-site bulk gas plant supplying most of ChangXin’s needs, while Zhiwei Semiconductor, a subsidiary of Zhichun Technology, provides wafer recycling capacity in Hefei’s Xinzhhan High-Tech Zone. State-owned venture capital has also taken direct controlling stakes in Wen Yi Technology, an upstream chip molding equipment supplier.

Second, Hefei’s state-owned capital is willing to sustain losses for a very long time. Unlike private equity funds that must deliver periodic returns to their LPs, Hefei’s state-backed venture investments are ultimately backed by municipal and development zone state-owned entities, with no exit timeline. They continued to inject capital into a company that only achieved its first annual profit in 2025 after accumulating losses of approximately 36.65 billion RMB over nearly a decade. The “506 Project,” launched in 2016, sourced about 80% of its initial funding (14.4 billion RMB out of 18 billion RMB) from Hefei’s state-owned capital. Although Hefei’s stake was diluted in subsequent funding rounds, it never reduced or exited its position. By the time of the IPO, the largest shareholder, Hefei Qinghui Jidian, held 21.67%, and state-backed venture investments collectively held over 30%. This willingness to treat a semiconductor fab as a decade-long bet rather than a fund-cycle return—this is the catalyst upon which both technology and talent depend.

When these three clues are combined, XMC’s first decade becomes clear. Qimonda provided the foundation: a patent portfolio and memory cell architecture from outside the big three. Talent provided the momentum: key figures like Kuesters and Ping, combined with returning expatriates from U.S. giants and controversial hires from Korea, turned frozen blueprints into a continuously advancing process. Then, the Hefei government supplied what the first two could not generate on their own: capital, patience, and a localized supply chain. All three were indispensable.

Next, discuss ChangXin's finances, technology, and equipment ecosystem.

Although Xinjiang's story over the past decade has been impressive, it may only be an early chapter in a much longer narrative. The company is preparing for one of China's largest semiconductor IPOs in recent years—and possibly the most closely watched semiconductor listing globally this year. In December 2025, the Shanghai Stock Exchange officially accepted Xinjiang's application for listing on the Sci-Tech Innovation Board. Prior market rumors throughout 2024 and 2025 had suggested the company was preparing for an IPO. The latest development is that Xinjiang submitted its registration application to the China Securities Regulatory Commission on May 27 and is currently in the final review stage.

ChangXin's IPO prospectus has disclosed a wealth of previously unavailable information. Combined with SemiAnalysis's Memory Model, it is possible to make a more accurate assessment of ChangXin's current position and future trajectory.

On a high level, by nearly all metrics, CXMT is the world’s fourth-largest DRAM manufacturer and is widening its lead over second-tier memory vendors. In full-year 2025, CXMT’s revenue grew 156% year-over-year to approximately $8.6 billion, up from about $3.3 billion in 2024 and $1.2 billion in 2023. Net profit also turned positive for the first time, reaching $1 billion. Even so, CXMT’s 2025 revenue remains significantly lower than the DRAM revenues of Samsung (~$72.3 billion), SK Hynix (~$52.1 billion), and Micron (~$37.2 billion).

Caption: Global DRAM Vendor Revenue Comparison (Source: SemiAnalysis Memory Model)

In the first quarter of 2026, CXMT reported revenue of $7.3 billion, a year-over-year increase of approximately 700%, with quarterly revenue nearing the full-year level of 2025. Operating profit margin also expanded sharply to approximately 70%.

SemiAnalysis believes this is just the beginning. Based solely on the prospectus disclosures, the company's revenue for the first half of 2026 is expected to grow sevenfold year-over-year, exceeding $16 billion. For the full year of 2026, SemiAnalysis estimates that XMC's revenue could surpass $50 billion. If achieved, this would mean the company has more than doubled its annual revenue every year since 2023, with a year-over-year growth rate exceeding sixfold in 2026.

The driver of this explosive growth is less about technology or market share and more about the cycle itself. Look closely at the data: In Q1 2026, CXMT’s bit shipments increased by only 11%, but its ASP (average selling price) rose by approximately 57%, following quarterly ASP环比 increases of 63% and 68% in Q3 and Q4 2025, respectively. What truly boosted performance was the explosive price increase, not a significant gain in market share over peers. According to SemiAnalysis’s model, CXMT’s market share, measured by bit shipments, is projected to rise from 9% in 2025 to 12% in 2027. While a 3-percentage-point increase in market share may seem modest, in a market SemiAnalysis forecasts to reach nearly $1 trillion in size by 2027, it is enormous.

Caption: ASP of CXMT versus bit shipment trends (Source: SemiAnalysis Memory Model)

For readers who have not closely followed CXMT or the memory market, a more interesting insight is the comparison between CXMT’s pricing and that of industry leaders. Based on Memory Model data, CXMT’s DRAM ASP challenges a common misconception: that Chinese memory products are structurally cheaper and therefore disrupt the market by driving down global prices. While this may have been true in certain past instances, it is not accurate in this cycle.

For the first quarter of 2026, CXMT's DRAM ASP is only about 5-10% lower than that of Samsung, SK Hynix, and Micron. SemiAnalysis expects this trend to persist throughout 2026, but the gap will gradually widen. The widening is not due to inherent pricing differences, but rather changes in product mix: leading vendors have a higher proportion of server DRAM and HBM shipments, and server DRAM has more favorable pricing prospects than consumer-grade DRAM.

By the end of 2027, SemiAnalysis expects server DRAM and HBM to account for more than 50% of DRAM end-market demand. Due to the higher per-GB pricing of server DRAM and HBM, leading manufacturers will further widen their ASP gap with CXMT, especially given the anticipated significant price increase for HBM in 2027.

Caption: DRAM manufacturer ASP comparison (Source: SemiAnalysis Memory Model)

Strong ASP tailwinds significantly improved CXMT's profitability. The full-year 2025 gross margin reached 37.8%, approaching Samsung's 39.4% and Micron's 39.8%, but still well below SK Hynix's 60.4% (benefiting from a higher HBM shipment mix). CXMT's gross margin of approximately 38% represents a massive improvement from -113% in 2023 and -4.7% in 2024. 2025 marked not only CXMT's highest gross margin on record but also the company's first-ever positive gross margin.

Caption: Gross margin comparison among DRAM manufacturers (Source: SemiAnalysis Memory Model, company reports)

Entering 2026, profit margins further improved. The operating profit margin in the first quarter reached 70%, compared with 73% for SK Hynix, 81% for Samsung, and 84% for Micron. In addition to ASP growth, CXMT’s margin improvement is also driven by its product mix, which is almost entirely focused on commodity DRAM—under current market conditions, commodity DRAM actually offers higher margins than HBM. According to the prospectus, approximately 99% of CXMT’s bit shipments in 2025 were traditional LPDDR and DDR products, with HBM contributing minimally to revenue and profits.

Caption: Comparison of operating profit margins among DRAM manufacturers (Source: SemiAnalysis Memory Model, company reports)

A simple DDR5 unit cost analysis provides greater clarity. SemiAnalysis found that CXMT’s DDR5 cost per bit remains over 30% higher than that of the three major players. However, due to the strong pricing of DDR5 in Q1 2026, CXMT’s gross margin has been pushed above 70%. This indicates that CXMT’s margin improvement is primarily driven by pricing, rather than substantial gains in product competitiveness or cost structure.

Caption: Cost per bit comparison for DDR5 (Source: SemiAnalysis Memory Model)

In addition to record profits, CXMT is also catching up in terms of production capacity. By the end of 2026, SemiAnalysis expects CXMT to reach approximately 350,000 wafers per month, just slightly below Micron’s approximately 385,000 wafers per month. Based on wafer capacity, CXMT is poised to become the third-largest memory manufacturer in the industry.

Caption: Monthly wafer capacity comparison among global DRAM manufacturers (Source: SemiAnalysis Memory Model)

However, CXMT still lags significantly behind the two giants: Samsung produces approximately 720,000 wafers per month, and SK Hynix produces about 595,000 wafers per month. By 2027, with the initial ramp-up of Phase 1 in Shanghai and full production in Hefei and Beijing, CXMT’s capacity is expected to reach around 420,000 wafers per month, accounting for approximately 17% of global DRAM capacity—up from about 13% in 2025. Measured by bit shipments, its market share is projected to rise from 9% in 2025 to 12% in 2027.

By 2028, with Hefei operating at full capacity and Shanghai’s two phases ramping up, SemiAnalysis expects CXMT to reach 500,000 wafers per month, accounting for approximately 17% of global DRAM supply.

Caption: CXMT Hefei facility capacity (Source: SemiAnalysis Memory Model)

Given that CXMT is playing an increasingly important role in global DRAM capacity, as has been the case in every previous cycle, investors are concerned that Chinese manufacturers could cause a supply-demand imbalance. SemiAnalysis believes this concern is significantly overstated for at least the next two years. Even after accounting for the incremental capacity and bit shipments from CXMT and other memory manufacturers, assuming utilization rates above 90%, DRAM supply remains extremely tight.

Caption: DRAM Supply and Demand Balance (Source: SemiAnalysis Memory Model)

Looking solely at ChangXin’s capacity expansion pace: in 2026, 2027, and 2028, it will add approximately 85,000, 70,000, and 80,000 wafers per month, respectively, while Samsung adds 15,000/50,000/110,000, SK Hynix adds 60,000/60,000/90,000, and Micron adds 30,000/90,000/115,000. Even accounting for these new capacity additions, DRAM will still face a high single-digit percentage shortage in 2026, with the gap expanding to a low-to-mid double-digit percentage in 2027. SemiAnalysis has previously detailed why DRAM may remain in sustained supply deficit through 2028.

XMC does not have the capacity to irrationally accelerate capacity expansion beyond its current pace to disrupt the market, as the construction cycle for fabs is too long. The currently extremely favorable pricing environment is precisely the main driver behind XMC’s performance surge—XMC naturally hopes this environment will continue. SemiAnalysis’s tracking of fab construction progress also shows no indication of such a possibility; however, it is important to note that the total wafer capacity of the Shanghai facility at full production can exceed 400,000 wafers per month.

Regarding HBM, XMC's wafer allocation is extremely limited. As of the end of 2025, out of XMC’s total capacity of approximately 2.65 million wafers per month, only about 5,000 wafers are allocated to HBM. SemiAnalysis estimates this will increase to approximately 30,000 wafers by the end of 2026 and about 55,000 wafers by the end of 2027. This aligns with the disclosure in the prospectus that approximately 99% of revenue in 2025 came from DDR and LPDDR.

Caption: CXMT HBM wafer capacity allocation (Source: SemiAnalysis Memory Model)

However, this allocation格局 may change. China’s push for autonomous and controllable AI computing power may conflict with the company’s commercial priorities, and this pressure is expected to intensify over time. SemiAnalysis has factored in government guidance directing ChangXin to shift capacity toward HBM, anticipating accelerated HBM capacity expansion in 2027 and 2028. ChangXin’s HBM capacity is projected to reach 55,000 wafers per month in 2027 and 100,000 wafers per month in 2028, increasing its share of global HBM wafer supply from 1% in 2025 to 12% in 2028.

It must be remembered that ChangXin is different from other memory manufacturers; it is not only a company of economic and technological importance but also a strategic asset that the state can leverage to advance priority policy objectives.

From a short-term business perspective, it is rational for CXMT to prioritize allocating capacity to bulk DRAM rather than HBM. Bulk DRAM currently offers significantly higher profit margins than CXMT’s HBM products, and it produces more than three times the number of bits per same wafer area. During the early stage of HBM technology development, dedicating substantial capacity to HBM would consume scarce wafer resources that could otherwise be used for bulk DRAM, which offers higher margins and greater volume. However, China must advance its HBM strategy, as HBM sales to China are strictly restricted by U.S. export controls, and Korean vendors’ shipments to China rely only on limited loopholes.

In terms of technical readiness, SemiAnalysis believes that CXMT is still struggling to achieve production stability for HBM3 8-hi, with 12-hi presenting even greater challenges.

On the front-end side, CXMT has made progress in stabilizing production at its **G4 node (equivalent to the 1z node)**, with the majority of DRAM output in 2026 expected to be based on the G4 process. However, DRAM core chips used for HBM, due to their larger die area and more stringent performance requirements, are likely to have significantly lower wafer-sort yields compared to commodity DRAM. SemiAnalysis believes front-end yield remains a major challenge for CXMT, with a substantial gap still existing compared to its peers. Although G4 yields have improved, based on lower profit margins observed in 2024 and 2025, they may still fall below the industry-standard mature yield level of 85–90% for the 1z node. This suggests that equipment limitations and manufacturing experience remain ongoing obstacles for CXMT to overcome.

Caption: CXMT DRAM process node roadmap and yield (Source: SemiAnalysis Memory Model)

The next-generation process node, G5 (equivalent to the 1a node), could theoretically continue advancing without reliance on EUV lithography, similar to Micron's 1a node, but will face increasingly significant manufacturing and design challenges. These challenges are further exacerbated when applying this node to DRAM dies for HBM.

Die stacking is the biggest challenge for CXMT's HBM. HBM stacking typically introduces significant technical challenges: thermal stress, die cracking, warpage, bonding defects, and yield loss due to multi-layer stacking. These issues become more severe when advancing from HBM3 8-hi to HBM3 12-hi and beyond to HBM3E, as CXMT still lacks sufficient manufacturing experience with 12-hi and higher HBM configurations.

Stacking challenges are not unique to CXMT. Leading manufacturers also face issues such as die cracking, thermal management, and yield loss with 12-hi HBM4. 16-hi and even 20-hi are even more difficult— one reason Rubin Ultra is expected to adopt 12-hi HBM4E instead of 16-hi is supply: 16-hi requires more DRAM wafers, is harder to manufacture, results in greater wafer loss, and provides fewer effective bits.

SemiAnalysis believes that CXMT is increasingly likely to skip HBM3 and focus directly on HBM3E 8-hi and 12-hi. There are two reasons: first, customers will need more competitive HBM products by the 2027 timeline; second, mainstream accelerators by then will be equipped with HBM3E, HBM4, and HBM4E.

Caption: Comparison of global HBM roadmaps (Source: SemiAnalysis Memory Model)

In terms of backend packaging, although there is still debate over whether ChangXin uses MR-MUF or TC-NCF, the packaging challenges are relatively more manageable, as the company and its packaging and testing partners face fewer restrictions under export controls. ChangXin has maintained close collaboration with leading OSATs such as Tongfu Microelectronics, and its backend capabilities are likely improving gradually, though it still lags behind top-tier memory manufacturers.

Based on existing manufacturing challenges, SemiAnalysis models the front-end and back-end yields for CXMT's HBM3 8-hi at approximately 35% and 70%, respectively, resulting in an overall yield of only about 25%. Due to higher stacking and bonding complexity, the overall yield for HBM3 12-hi or HBM3E 12-hi is likely even lower. At these yield levels, CXMT’s HBM output per wafer is significantly lower than that of leading manufacturers. More critically, the profitability of the produced HBM is extremely low, especially when compared to bulk DRAM under current pricing conditions.

The challenges facing CXMT's HBM are also reflected in its product adoption. SemiAnalysis believes that only Huawei, Cambricon, and a few emerging Chinese AI chip startups may adopt CXMT's HBM, though adoption rates among these companies could be high. Domestic AI accelerator manufacturers still prefer to use foreign HBM3 or even HBM3E whenever possible, whether through any available channels or inventory accumulated before the export controls took effect in December 2024. As China's domestic cloud providers rapidly increase their capital expenditures and compute infrastructure construction, demand for domestic HBM is also growing swiftly.

A notable exception: Huawei and CXMT will develop custom HBM that does not rely on JEDEC standards or PHY, helping to compensate for the bandwidth disadvantage.

The HBM supply constraints facing China may be more severe than what the slower development of domestic HBM suggests. The supply from the three major HBM vendors is already tight, and under U.S. export controls as of December 2024, they are restricted from selling HBM2E and more advanced HBM products to China. In this environment of tight supply, these vendors have even less incentive to risk violating these restrictions to sell to China.

However, the re-export and smuggling of HBM have complicated the situation. SemiAnalysis has learned that some Chinese companies continue to acquire HBM through various channels. Re-export via overseas offices or third-country partners remains a viable pathway; some third-country OSATs or intermediaries are facilitating these flows. Certain entities export systems or modules in partially assembled form (not classified as finished GPUs or ASICs, and thus still permitted for export to China), after which the HBM is disassembled and repackaged onto domestically produced GPUs or ASICs.

ChangXin may become one of China's largest semiconductor IPOs, and its equity structure is more noteworthy than its reported financials. ChangXin reported a consolidated net profit of RMB 7.14 billion for 2025, but net profit attributable to shareholders of the parent company was only RMB 1.87 billion, with 74% attributable to minority interests.

The reason lies in the equity structure. ChangXin holds only 30.68% economic interest in ChangXin XinQiao and 31.72% economic interest in ChangXin Jidian Beijing, but exercises voting control of 73.01% and 75.32% respectively through long-term acting-in-concert arrangements. This allows the company to consolidate fabs it does not actually own, thereby overstating the profits available to public shareholders by approximately fourfold.

Caption: CXMT Consolidated Profit vs. Net Profit Attributable to Parents (Source: SemiAnalysis Memory Model, Company Reports)

The same voting structure also undermines the credibility of the company’s claim of having “no controlling shareholder or actual controller” (listed in the prospectus as a formal governance risk). ChangXin exercises majority voting control over the wafer fab through a concert party agreement, and after the listing, the National Integrated Circuit Industry Investment Fund II, along with state-owned entities in Hefei and Anhui, collectively hold more than 30% of the shares. This arrangement appears designed to manage export controls and perceptions among foreign investors, at a time when ChangXin’s relationship with the Chinese government is under the most scrutiny.

Caption: CXMT equity structure diagram (Source: SemiAnalysis Memory Model, company reports)

ChangXin plans to raise RMB 29.5 billion (approximately $4.1 billion), representing 10-15% of its total shares after listing. A full IPO financing implies a price of approximately RMB 4.41 per share at 10% dilution and RMB 2.78 per share at 15% dilution (the financing price in June 2025 was RMB 2.63). The lower end of this pricing range reflects almost no premium over the previous round, despite achieving $7.3 billion in revenue and $4.8 billion in net profit in Q1 2026. A price of RMB 2.78 corresponds to a valuation of approximately RMB 197 billion (about $27 billion), equivalent to just 1.8 times the annualized attributable profit for the first half of 2026. SemiAnalysis believes this valuation floor is far too low and that the actual pricing should be significantly higher.

Caption: CXMT IPO Valuation Analysis (Source: SemiAnalysis Memory Model, Company Reports)

The allocation of RMB 29.5 billion reinforces ChangXin’s current priorities. Of this, RMB 20.5 billion (69.5%) is designated for wafer production lines and DRAM technology upgrades, while RMB 9 billion (30.5%) is allocated to forward-looking DRAM research. The prospectus does not disclose any dedicated HBM project, nor does it mention HBM at all. The project descriptions focus on newer process platforms, product iterations, and the migration of existing production lines toward mid- to high-end DRAM. The core purpose of the IPO is to strengthen ChangXin’s DRAM manufacturing and technological foundation, with no public commitment of funding for near-term HBM expansion.

Caption: Allocation of CXMT IPO proceeds (Source: SemiAnalysis Memory Model, company reports)

The magnitude of profit variation requires a reminder about cyclical timing. ChangXin projected a full-year net loss of RMB 600 million to 1.6 billion in its prospectus dated December 2025. Five months later, an updated prospectus reported a profit of RMB 1.87 billion—more than double the previous high-end estimate. This also illustrates how quickly DRAM pricing at its peak can alter valuation multiples—in either direction.

The final detail: Alibaba’s role on ChangXin’s shareholder list has changed the interpretation of ChangXin’s demand side. Alibaba Cloud is both a core hyperscale customer and a shareholder with nearly 4% ownership and endorsement, alongside Zhu Yiming’s GigaDevice (holding approximately 1.8%). Domestic demand volume has, to some extent, been secured—an advantage that Korean giants do not enjoy in their home market. Although the percentage is small, its significance is much greater.

Note: The in-depth analysis of the CXMT device ecosystem, export control impacts, and China’s storage and computing ambitions in the latter part of this article is paid content from SemiAnalysis and is not included in this translation.