CXMT has recently made significant progress in the development of its 4F² DRAM architecture. At the 4th Integrated Chip and Chiplet Conference, CEO Dr. Cao Kanyu delivered a comprehensive presentation on CXMT’s technological advancements and accumulated expertise in DRAM devices, 4F² architecture, and hybrid bonding. He officially announced that the company expects to launch a new generation of DDR5 RDIMM products by year-end, integrating these advanced technologies.
According to Dr. Cao Kanyu, CXMT initiated research and patent landscaping for 4F² architecture since its founding, with over 300 publicly disclosed patent families—leading both domestic and international manufacturers. In 2021, CXMT published the first paper in mainland China on 4F² architecture, and further shared its R&D progress on this architecture in two additional papers in 2023 and 2025.
According to IT Home, the current industry-standard DRAM cell architecture is 6F². In DRAM chip design, each memory cell typically consists of one transistor (1T) and one capacitor (1C). A 4F² design means each cell occupies only four times the square of the minimum feature size, thereby increasing storage density. The transition from 6F² to 4F² represents a fundamental change, as the existing 6F² process cannot be directly reused and requires an entirely new device and process architecture.
During development, CXMT conducted in-depth technical research and breakthroughs across multiple core process steps, comprehensively optimizing critical processes including word line metallization, bit line formation, and junction activation to achieve optimal performance-to-power ratios.
The speech did not mention the specifications or release date of CXMT’s upcoming DDR5 RDIMM. However, as DDR5 RDIMM is the mainstream configuration in the server market, this means CXMT has chosen its first-generation product based on the 4F² architecture to be a DDR5 RDIMM, directly confronting the extremely high technical and engineering barriers in the server memory sector.