Domestic computing power is transitioning from "catching up in performance" to "systemic rise."Article author and source: Wall Street Journal
The domestic computing power theme is no longer just a single issue of “which chip has caught up in performance.” More crucially, it hinges on three key factors: whether domestic AI chips can be delivered at scale, whether advanced manufacturing can meet the demands of mass production, and whether, when single-card performance is limited, super-node architectures can effectively combine multiple cards’ computing power into truly usable system-level compute.
On July 21, Xue Hongwei, an industry analyst at Guolian People's Securities, wrote in a sector research report: “Currently, both supply and demand sides of China’s domestic computing power industry are showing significant growth, and the rise of domestic computing power has become one of the key trends in industrial development. We recommend focusing on the ‘three arrows’: chips, FABs, and super nodes.” This framework breaks down the core challenges of China’s domestic computing power: demand is rising, supply must catch up, and system architecture must also be upgraded.
Demand-side changes are straightforward: domestic large models continue to iterate, token usage volumes are growing rapidly, and leading cloud providers are further directing capital expenditures toward AI. On the supply side, access to overseas high-end AI chips and advanced manufacturing pathways remains restricted, increasing pressure for domestic alternatives. In 2025, total shipments of AI accelerators in China are projected to reach approximately 4 million units, with domestic AI chips accounting for about 1.65 million units—marking the first time their market share exceeds 40%.
Under this framework, chips represent the front-end leverage for scaling; wafer foundries form the foundation of capacity and process; and super-nodes address the question of how to strengthen the system when a single card isn’t powerful enough. Investment opportunities thus expand from AI chip manufacturers to include wafer foundries, PCIe switches, Ethernet switching chips, high-speed SerDes, optical communications, and integrated system solutions.
Domestic AI Chips: From Product Validation to Large-Scale Delivery The alignment between domestic large models and domestic chips is accelerating. In April 2026, DeepSeek V4 was released and open-sourced, with successful adaptations completed on domestic chips including Hygon, Huawei Ascend, Kunlun芯, and Moore Threads. In July, Meituan’s LongCat-2.0 was open-sourced—a trillion-parameter model trained end-to-end on a domestic computing cluster of 50,000 accelerators, with a total of 1.6 trillion parameters and an average activation of approximately 48 billion, demonstrating that collaborative training of domestic large models on domestic computing infrastructure is feasible.
Token usage is the most critical metric on the demand side. According to OpenRouter data, between March 16 and 22, 2026, the platform’s weekly token usage reached 20.4 trillion, a 20.7% increase week-over-week; the weekly average in February 2026 had already more than doubled the quarterly average of Q4 2025. Agent scenarios further amplify compute consumption: a single agent consumes approximately four times the tokens of a typical conversation, while multi-agent collaborative systems can reach up to 15 times.
Cloud providers' capital expenditures are also following this trend. In Q1 2026, the combined capital expenditure of BAT increased by 17.7% year-over-year to RMB 64.746 billion, up 28.03% sequentially from Q4 2025. ByteDance raised its 2026 capital expenditure plan to RMB 160 billion, with approximately RMB 85 billion allocated directly toward AI chip purchases; Alibaba announced plans to invest RMB 380 billion over the next three years in cloud and AI infrastructure; Tencent's operating capital expenditure in Q1 2026 reached RMB 31.2 billion, up 18% year-over-year and 84% sequentially.
On the supply side, domestic AI chip manufacturers are expanding their product portfolios. Huawei Ascend is expected to ship approximately 812,000 units in 2025, accounting for nearly 50% of domestic AI chip shipments, with future roadmaps planned for Ascend 910C, 950PR, 950DT, 960, and 970. Cambricon covers cloud training, cloud inference, and edge scenarios; the MLU590 is built on a 7nm process and delivers 512 TOPS of INT8 computing power. Hygon focuses on "general-purpose computing + AI integration," with its Shenlong DCU compatible with a CUDA-like environment. Moxi's MXC600 emphasizes integrated training and inference, utilizing a fully domestic supply chain. Tenstorrent covers three major series: training, inference, and edge computing.
ASIC is also a distinct line worth examining separately. Cloud-side compute demand is no longer solely reliant on general-purpose GPUs; chips customized for specific models, algorithms, and use cases offer superior energy efficiency and greater cost-control potential in inference and high-performance data center computing scenarios. Verisilicon, leveraging its platform capabilities of “IP licensing + chip customization services + chip mass production services,” has already seen clear evidence in its order book: as of April 20, 2026, its outstanding orders reached RMB 5.133 billion, continuing the trend of consecutive record-breaking highs from Q2 to Q4 2025, with the majority stemming from its one-stop chip customization business, primarily driven by cloud-side AI ASICs and IP.
Foundry: The more advanced manufacturing is restricted, the more critical domestic foundational capabilities become. For domestic AI chips to move from validation to delivery, semiconductor manufacturing cannot be avoided. Over the past few years, the United States has continuously strengthened export controls on advanced computing chips and semiconductor manufacturing capabilities, incorporating logic chips at 16/14nm and below into its advanced node-related control framework and restricting the export of advanced semiconductor manufacturing equipment.
The demand-side opportunity is equally clear. According to the China Academy of Information and Communications Technology and Insight Consulting, China’s intelligent computing chip market is projected to grow from $30.1 billion in 2024 to $201.2 billion in 2029, with a CAGR of 46.3% between 2024 and 2029; the GPGPU market is expected to achieve a CAGR of 49.0% over the same period. Beyond AI chips, Huawei has proposed the "Taolü Law," predicting that by 2031, transistor density on high-end chips following this trajectory could reach levels equivalent to a 1.4nm process.
SMIC is the key focus in this segment. In the first quarter of 2026, the company achieved revenue of RMB 17.62 billion, an 8.1% year-over-year increase; net profit attributable to shareholders was RMB 1.36 billion, up 0.4% year-over-year. Revenue from 12-inch wafers accounted for 76.4%, while revenue from China accounted for 88.9%. Monthly capacity reached 1.078 million 8-inch wafer equivalents, up approximately 10.8% year-over-year, with a capacity utilization rate of 93.1%, remaining at a high level.
Hua Hong's data demonstrates the resilience of its specialized process platforms. In the first quarter of 2026, the company achieved revenue of $660 million, a 22.2% year-over-year increase; a gross margin of 13.0%, up 380 basis points year-over-year; and attributable net profit of $20.9 million, a 458.1% year-over-year increase. Revenue from 12-inch wafers rose to 62.7%, equivalent to a monthly capacity of 489,000 8-inch wafers, with a capacity utilization rate of 99.7%.
Jinghe Integration continues to expand its 12-inch specialty process platform. In the first quarter of 2026, the company's revenue reached RMB 2.91 billion, a 13.4% year-over-year increase; net profit attributable to shareholders was RMB 50.66 million, a 62.6% year-over-year decline, impacted by falling product prices and increased fixed asset depreciation. DDIC remains the core business, while CIS, PMIC, and Logic segments are gradually expanding. The 28nm OLED product is undergoing continuous validation, and the 28nm logic process platform has been completed and entered the customer tape-out phase.
Super Nodes: It’s not merely about stacking more GPUs; the performance of a single card is no longer sufficient to determine the actual performance of an AI cluster. As large model parameter scales grow and architectures evolve—such as with MoE and longer context lengths—the demands on memory bandwidth, inter-chip communication, and interconnect latency have significantly increased. The importance of scale-up has therefore risen: by connecting more AI processors, CPUs, memory, and storage resources via high-speed interconnects into a unified computational resource, multi-GPU collaboration efficiency is enhanced.
A super-node is a further evolution beyond scale-up architecture. It connects multiple server nodes via high-speed interconnects to form a unified computing domain, enabling AI processors distributed across different servers to collaborate as a single unit. Compared to traditional server clusters, which treat individual machines as the unit of resource management, super-nodes overcome the limit on the number of AI processors that can be deployed on a single server, reduce inter-node communication overhead, and improve resource scheduling efficiency.
Huawei CloudMatrix 384 is one of the representative solutions. This architecture is based on 384 Ascend NPUs and 192 Kunpeng CPUs, shifting from server-level resource provisioning to matrix-level resource provisioning. Multiple compute nodes no longer provide computing power individually but instead form a unified resource pool, enabling dynamic allocation of compute, memory, and network resources according to task requirements. Its Unified Bus supports communication-intensive tasks such as expert parallelism and distributed KV Cache access.
Domestic super nodes have transitioned from R&D validation to mass production scaling. Currently, domestic CSP super nodes are entering the mass production scaling phase, with leading manufacturers gradually initiating subsequent super node tenders. With major companies iterating on their self-developed chips, increased production capacity of third-party domestic chips, and growing demand for Agent inference, super nodes are poised to become the primary deployment form of the next-generation AI infrastructure.
The role of system integrators is also evolving. Super-node cabinets equipped with the Ascend 950 and proprietary chips from major internet companies are expected to gradually enter large-scale delivery. Super-nodes raise the barriers in supply chain management, system design, integration validation, and delivery, transforming system integrators from mere assembly and delivery providers.
High-speed interconnection has become the new bottleneck, pushing switching chips to the forefront. The core of a super-node is not “more GPUs,” but “more efficient interconnection.” As GPU clusters scale from GB300 NVL72 to Rubin Ultra NVL576, AI infrastructure is shifting from traditional scale-out models toward a coordinated approach combining scale-up and scale-out. Scale-up enables high-bandwidth, low-latency interconnection between GPUs within a super-node, while scale-out manages interconnection between super-nodes and at the data center level.
According to LightCounting data, the global scale-up switching chip market is projected to reach nearly $18 billion by 2030, with a compound annual growth rate of 28% from 2022 to 2030. Domestic AI servers are also driving demand for PCIe switching chips; based on information disclosed by Wantong Development, the domestic AI server PCIe switching chip market size was approximately RMB 3.8 billion in 2024 and is expected to grow to RMB 17 billion by 2029.
The PCIe switch is a critical chip within servers, enabling high-bandwidth, low-latency data exchange between components such as CPUs, GPUs, and storage devices.澜起科技 has launched its PCIe 6.x/CXL 3.x AEC solution and is developing next-generation products including PCIe 7.0 retimers and high-speed Ethernet PHY retimers; Shudu Technology has achieved mass production of its self-developed PCIe 5.0 104-lane high-speed switch chip; and Verisilicon is accelerating its deployment in interface-related IP, with its high-speed SerDes interface IP already taped out.
Ethernet switching chips are responsible for high-speed packet switching and forwarding over a larger scale. Starcore Communications' high-end flagship chips, offering 12.8 Tbps and 25.6 Tbps capacities, have entered the market promotion and application phase, supporting port speeds of up to 800 Gbps. ZTE Microelectronics will launch its self-developed AI switching chip, "Lingyun," in 2025, capable of supporting AI computing clusters ranging from tens of thousands to hundreds of thousands of accelerators. It will also showcase its Tianyi series Ethernet switching chips with a maximum switching capacity of 12.8 Tbps.