Celero Communications, a semiconductor startup barely a year old, has raised $140 million in total funding, with a $100 million Series B round led by Alphabet’s growth fund CapitalG. The company is building coherent digital signal processor chips purpose-built for AI data centers, targeting the increasingly painful problem of moving data between GPU clusters separated by real physical distance.
The Irvine, California-based company, which employs roughly 30 people according to PitchBook, announced the funding on November 17, 2025. Earlier seed and Series A rounds brought in $40 million from Sutter Hill Ventures, Valor Equity Partners, Atreides Management, and Maverick Silicon.
What Celero actually builds
Coherent DSP chips translate optical signals into electrical signals and back again, allowing data to travel long distances over fiber optic cables. Celero’s pitch is that existing telecom-grade coherent DSPs are overbuilt for data center distances while short-reach alternatives can’t cover the gaps between buildings in a campus-scale AI cluster. The company is designing chips that sit in the sweet spot: optimized for the specific distances, bandwidth demands, and power envelopes that AI data centers actually need.
The team behind the chips
Celero was founded in 2024 by Nariman Yousefi and Oscar Agazzi, two veterans of the semiconductor industry who previously worked at Marvell, Inphi, and Broadcom. Between them, they’ve shipped multiple generations of DSPs and networking integrated circuits.
Why AI networking chips are suddenly a hot market
As AI clusters scale from thousands to tens of thousands of accelerators, the networking fabric connecting them becomes a binding constraint. This is the same reason Nvidia has invested heavily in its own networking stack through the acquisition of Mellanox.
Celero isn’t the only startup chasing this opportunity. The broader market for AI data center interconnects is drawing interest from both established players like Broadcom and Marvell and newer entrants. Both companies already sell coherent DSPs for telecom applications.
Semiconductor development cycles typically run 18 to 24 months from design freeze to volume production. With roughly 30 employees and $140 million in the bank, the company has capital but will need to scale its engineering team significantly to hit those milestones.