Bernstein Report: AI Drives CPU Demand; Memory Interface Chip TAM to Triple to $20 Billion by 2030

Written by: Rita

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Bernstein released an in-depth introductory report on memory interface chips on July 9, noting that AI is evolving from training-intensive to inference-intensive, with CPUs once again becoming the core orchestrators in AI agent workloads, driving structural growth in server CPU shipments. The report significantly raised its forecast for the global memory interface chip TAM to $20 billion by 2030 (up from approximately $7 billion previously), corresponding to a five-year CAGR of 65%. The A-share target price for Jinan Technology was raised from RMB 220 to RMB 400, and the H-share target price was raised from HKD 320 to HKD 520, with both maintaining an "Outperform" rating. Renesas Electronics' target price was set at JPY 6,300, also maintaining an "Outperform" rating.

Bernstein believes that the memory interface chip market is entering a rare window where three structural tailwinds are aligning simultaneously.

The first layer is the accelerating growth in server CPU shipments. In AI agent workloads, CPU responsibilities such as task scheduling, KV cache management, and real-time security checks can account for 50% to 90% of total task completion time. AMD recently doubled its forecast for the global x86 server CPU TAM by 2030 to $120 billion, confirming this trend. Bernstein expects global server CPU shipments (excluding NVIDIA's proprietary CPUs) to rise from 30.6 million units in 2025 to 89.3 million units in 2030, representing a 24% compound annual growth rate.

The second layer is the continuous increase in the number of DRAM modules per CPU. To maximize accelerator utilization, AI servers typically achieve DIMM slot utilization rates of 70% to 80%, significantly higher than the approximately 50% seen in general-purpose servers. As CPU channel counts evolve from 8 channels to 12 and 16 channels, the demand for memory interface chips per CPU directly doubles.

The third layer is the significant increase in value per module brought by MRDIMM upgrades. MRDIMM uses an architecture of “1 MRCD + 10 MDBs,” whereas traditional RDIMMs require only 1 RCD. The value of the memory interface chip per module surges from approximately $7 to $70–$80, an increase of about 10 times. Bernstein expects MRDIMM penetration to rise from around 3% in 2026 to 25% by 2030.

The threefold drivers create a multiplier effect rather than a simple sum. Bernstein raised the 2030 TAM from approximately $7 billion to $20 billion.

The most common question in the market is: LRDIMMs never exceeded 1% penetration during the DDR4 era—what makes MRDIMMs different?

Bernstein outlined three structural differences. First, LRDIMMs address the error issue—they increase capacity without boosting bandwidth, whereas capacity was not a bottleneck in the DDR4 era. M RDIMMs address both capacity and bandwidth simultaneously; their multiplexed architecture doubles module bandwidth, directly tackling the bandwidth bottleneck of AI workloads. Second, RDIMMs were “good enough” in the DDR4 era, but they can no longer maintain signal integrity at speeds above 8,800 MT/s in DDR5; the migration to MRDIMMs is driven by physical laws, not marketing. Third, neither Intel nor AMD has released a product roadmap for DDR5 LRDIMMs, while MRDIMMs have received clear support from both major CPU platforms.

Additionally, AI servers have created a customer base that did not exist in the DDR4 era; these servers populate all DIMM slots and push each specification to its limits, making them the most natural customers for MRDIMMs designed for maximum bandwidth. Rising DRAM prices are also narrowing the cost gap between MRDIMMs and RDIMMs, further reducing migration barriers.

The memory interface chip market is a textbook example of an oligopoly. Together, Renesas (approximately 37%), Jiangsu Jinke (approximately 36%), and Rambus (approximately 20%) account for approximately 92% of the global market share.

The barriers to entry are extremely high. JEDEC standard certification requires chips to pass validation by multiple parties, including DRAM manufacturers, CPU platforms, module makers, and CSPs—a process that typically takes 18 to 24 months. Any design flaw or interoperability failure can result in a supplier being completely eliminated. Additionally, RCDs and MRCDs are the most technically complex components in DIMM chipsets, manufactured using state-of-the-art CMOS processes: DDR4 RCDs are produced on a 40nm platform, while first-generation DDR5 RCDs began at 28nm and are expected to evolve toward sub-10nm nodes in the future. All three suppliers are deeply involved in JEDEC standards development, with Renesas and Jinke serving as JEDEC Board members—thereby not only defining the standards but also establishing the high thresholds that new entrants must overcome.

In the MRDIMM space, Jiangsu Jinlong and Renesas lead the first-generation products, while Rambus opted to skip the first generation and directly enter the second. Competition in the second-generation MRDIMM (12,800 MT/s) will be more balanced.

Bernstein raised the A-share target price for澜起 to RMB 400 (previously RMB 220), based on a 50x forward P/E for Q3 2027 to Q2 2028; the H-share target price is HKD 520 (previously HKD 320), implying an approximately 15% premium over the A-share price.

The H-share premium reflects global investors viewing澜起 as a rare Chinese AI exposure, unlike other Chinese semiconductor companies that face direct geopolitical risks such as entity list restrictions or export controls. Due to lock-up periods limiting the float, the premium is expected to be sustained in the short term.

Montage's growth is driven by three factors: increased penetration of MRDIMMs leading to higher volumes of interface chips, rising CPU shipments driving greater demand for memory interfaces, and contributions from new businesses such as PCIe Retimers. Bernstein expects Montage's EPS to reach RMB 5.68 and RMB 10.82 in 2027 and 2028, respectively.

The core insight of Bernstein's report is that memory interface chips are transitioning from secondary components that follow DRAM cycles to direct beneficiaries of AI compute expansion. The reevaluation of the CPU's role in the age of AI agents—from a bystander during training to the central conductor during inference—serves as the foundation of this logic. The multiplicative effect of three converging drivers has propelled the TAM from approximately $7 billion to $20 billion, a magnitude of growth that is extremely rare in semiconductor sub-sectors.

Whether MDRDIMM succeeds is the key variable in validating the entire story. The failure of LRDIMM taught us that technological upgrades must simultaneously address real bottlenecks (bandwidth, not capacity), gain clear support from CPU platforms, and have a sufficiently large customer base. The explosion of AI servers has precisely met all three conditions.

The premium of澜起’s H-shares relative to its A-shares is worth noting. The premium, driven by limited liquidity in the Hong Kong market, may persist in the short term but faces a risk of narrowing after the lock-up period ends. For A-share investors,澜起’s scarcity logic and the H-share premium logic are essentially opposite: A-shares carry no geopolitical discount but also miss out on the scarcity premium of H-shares. The dynamic evolution of the price differential between the two markets itself constitutes a trading signal worthy of continuous monitoring.

Disclaimer

This article is a summary and interpretation by Chaoxiang Research of a third-party brokerage research report (Bernstein, July 9, 2026). The ratings, target prices, earnings forecasts, and related judgments cited herein reflect the views of the brokerage’s analysts and represent the position of their respective institution only; they do not reflect the views of Chaoxiang Research nor constitute any investment advice.

The market carries risks; make decisions independently. This article should not be used as a basis for buying or selling any securities.