ASML is developing hybrid bonding equipment, focused on chip-to-wafer applications.

Huo Xing Cai Jing reports that on October 15, semiconductor research firm SemiAnalysis published an article stating that although lithography equipment maker ASML has not officially announced any related products, patents, news reports, and company roadmaps all indicate that it is developing hybrid bonding equipment. The article’s author suggests that ASML may first launch the more challenging chip-to-wafer hybrid bonding tool, viewing it as an extension of vertical integration. Patents reveal that the system operates on a track, with each chip placed on an individual carrier and sequentially processed through inspection, cleaning, plasma activation, topography measurement, leveling, coarse alignment, position adjustment, and fine alignment before entering the bonding station; final placement is achieved by the carrier and vacuum chuck. The track’s repeatability is approximately 10 micrometers—far short of the ~50 nanometers required for bonding. Between December 2022 and November 2024, ASML filed 27 patent families related to bonding, most targeting chip-to-wafer applications. In March, The Elec reported that ASML has begun architectural design for hybrid bonding machines in collaboration with Prodrive Technologies and VDL ETG. The article notes that wafer-to-wafer hybrid bonding is already used in image sensors and 3D NAND; chip-to-wafer bonding is currently used only for mass production of logic chips, including AMD’s hybrid-bonded V-Cache products shipped since 2022 and TSMC’s SoIC. SoIC currently achieves a pitch of approximately 6 micrometers, with a target of 4.5 micrometers by 2029. Besi is currently the only supplier with chip-to-wafer mass production tools, with its logic business primarily focused on TSMC and Intel.