Apple Unveils M6 Chip with TSMC’s 2nm Process, Driving Demand for Advanced Packaging

HuoXing Finance reports that Apple has officially unveiled its first 2-nanometer M6 chip, featuring a 12-core CPU, 12-core GPU, and dual 16-core neural engines, with a unified memory bandwidth of up to 170 GB/s, initially deployed in the new Mac mini. Manufactured using TSMC’s 2-nanometer process, the chip is the world’s first consumer-grade 2-nanometer chip to adopt gate-all-around (GAA) nanosheet transistors. The supply chain is closely monitoring the upcoming high-end M-series packaging architectures. Building on the Fusion Architecture of the previous M5 Pro and M5 Max, as well as the quad-die design of the M5 Ultra, Apple’s chips have transitioned from single large dies to modular designs. Future M6 Pro, Max, or Ultra variants are expected to drive increased demand for advanced packaging technologies such as SoIC-MH and WMCM—using SoIC-MH to enhance interconnect density and WMCM to integrate logic, LPDDR memory, and high-speed I/O. TSMC is actively preparing for capacity expansion: its Zhunan AP6 facility is the primary production site for SoIC, its Longtan AP3 facility is being upgraded for WMCM, and its Jiayi AP7 facility will handle related capacity. Industry analysts estimate WMCM monthly capacity will reach approximately 60,000 wafers by the end of 2026 and exceed 120,000 wafers in 2027. Equipment manufacturers such as Hongsu, Junhua, and Yineng, as well as materials suppliers including Changxing, Xinyingcai, and Yongguang, are expected to benefit.