AMD Reveals 2nm Server Processor Roadmap, Targeting 2027 Mass Production

ChainCatcher report: AMD disclosed details on server processors and die interconnect layouts at the In Depth Technology Forum. Venice utilizes TSMC’s N2 process and CoWoS-L advanced packaging, incorporating Elevated Fan-Out Bridge (EFB); subsequent Verano will adopt the N2P process. AMD’s Server Architecture Lead, Mahesh Subramony, stated that as compute cores increase, more data must be transmitted between dies, and EFB reduces power consumption and latency through short-distance interconnects. AMD expects the data center CPU market to grow from approximately $26 billion in 2025 to around $220 billion by 2030, with a compound annual growth rate exceeding 50%. In packaging collaboration, ASE and SPIL are involved in the development and validation of wafer-level 2.5D bridge interconnects, while AMD and Powertech have completed panel-level EFB interconnect validation. In May 2026, AMD announced an investment of over $10 billion in Taiwan’s industrial ecosystem to expand strategic partnerships and advanced packaging capabilities. On product progress: the Venice SP7 platform has begun shipping; the SP8 platform targeting enterprise markets is expected to be available in the first half of 2027; Verano and Venice-X are scheduled for release in the second half of the same year, with all related server processor products targeting mass production in 2027.