XCENA Raises $135M in Series B Round, Targets AI Memory Bottlenecks

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XCENA, a U.S.-South Korea chip startup, raised $135 million in a Series B round, reaching a $570 million valuation. The company is addressing AI inference costs by redesigning memory architecture. Its MX1 chip prototype reduces data transfer between the CPU, GPU, and memory by moving computation closer to DRAM. XCENA plans mass production by late 2026 and is targeting hyperscale cloud providers. As AI and crypto news gains momentum, XCENA’s approach aligns with growing demand for efficient computing. Inflation data remains a key factor for investors monitoring tech funding trends.
CoinDesk reports:

Competition in AI infrastructure is expanding from GPUs to memory. XCENA, a chip startup operating in both South Korea and the United States, has completed a $135 million Series B round, bringing its post-money valuation to $570 million. The company believes that cost pressures in generative AI during inference stem not only from compute chips but also from the constant data movement between CPUs, GPUs, and memory.

Post-financing valuation rises to $570 million

Following this funding round, XCENA has raised a total of $185 million. The company was co-founded by CEO Jin Kim, CTO Dohun Kim, and CPO Harry Juhyun Kim, all of whom previously worked at Samsung Electronics and SK Hynix—two of the world’s leading memory chip suppliers and key players in NVIDIA’s GPU supply chain.

TechCrunch reports that XCENA believes AI inference is shifting from a "compute problem" to a "memory scaling problem." As models generate each token by invoking context, caching, and preprocessing workflows, data is constantly transferred back and forth between chips, resulting in additional latency, power consumption, and hardware costs.

The chip moves part of the computation closer to the memory.

XCENA's product, named MX1, is currently in the prototype stage. This chip connects to the CPU via CXL and relocates certain data processing tasks closer to DRAM, reducing data往返 between the CPU, GPU, and memory.

The company says such tasks include preprocessing, KV cache management, and data caching. According to them, work that would typically require 10 servers may, under specific scenarios, be consolidated onto a single server. However, this effect still needs validation through large-scale deployment.

Plan to begin mass production by the end of 2026

XCENA expects its mass-production chips to come off Samsung's foundry lines by the end of 2026 and begin generating revenue in 2027. The company’s current target customers are hyperscale cloud providers that invest tens of billions of dollars annually in AI infrastructure, as even a modest improvement in memory efficiency could result in hundreds of millions of dollars in cost savings.

The company stated that since the second half of last year, market demand for memory-related solutions has significantly increased, and it has already initiated early discussions with several global memory manufacturers, though it has not disclosed specific names.

Competitors include Astera Labs and Marvell.

In the competitive landscape, XCENA considers Astera Labs and Marvell as close peers. Both companies are advancing next-generation memory interconnect solutions, with Marvell being an established public company.

XCENA believes its key differentiator lies in the internal architecture of its chips. The company states that its solution is based on RISC-V, utilizing numerous small data processing cores, along with proprietary memory hierarchies, interconnect buses, and DRAM controllers—rather than outsourcing these components to third parties.

This round of funding was co-led by South Korean venture capital firms Altinum and IMM Investment, with participation from Corstone Asia and existing shareholders SBI Investment and Mirae Asset Capital. XCENA currently has offices in Banqiao, Korea, and Sunnyvale, USA, with over 90 employees total, and is in discussions with international investors regarding future funding.

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