SemiAnalysis: SPHBM4 Standard May Ease AI Packaging Bottlenecks and Benefit the Substrate Industry

Huo Xing Finance reports that on July 3, the semiconductor and AI independent research firm SemiAnalysis published a statement noting that JEDEC last week announced the new SPHBM4 standard, also known as JESD330-4: Standard Packaged High Bandwidth Memory. SPHBM4 uses the same DRAM stack as HBM4 but replaces it with a different buffer chip, aiming to enable HBM assembly within a standard package and alleviate bottlenecks in advanced AI packaging. The concept behind SPHBM4 is to maintain HBM4 performance while significantly reducing reliance on expensive and scarce advanced packaging technologies. SPHBM4 presents a major opportunity for the substrate industry. On one hand, traditional HBM must be placed extremely close to the GPU because wide parallel signals attenuate rapidly over distance; SPHBM4, however, employs high-speed serial channels, allowing memory to be positioned up to 20 millimeters away. With increased packaging area, the total substrate material required per chip will rise substantially. On the other hand, transmitting 32 Gbps signals directly through organic substrates increases electrical complexity; SPHBM4 will drive adoption of high-end, high-density ABF substrates with 20 to 28+ layers—and eventually glass substrates in the future. The firm stated that SPHBM4 will shift the complex engineering burden of AI chips away from the “silicon interposer + ABF substrate” combination toward much larger, higher-layer ABF substrates—and even accelerate the adoption of glass substrates. “The substrate boom has only just begun.”