AMD's 6th Generation EPYC Venice Processor Enters 2nm Production at TSMC

AIMPACT Update: On May 21 (UTC+8), according to monitoring by Beating, AMD’s sixth-generation EPYC processors (codenamed Venice) have begun mass production on TSMC’s 2nm node at its wafer fabrication facility in Taiwan. This marks the industry’s first high-performance computing (HPC) product mass-produced using TSMC’s 2nm process. In response to the surging memory demands of agentic AI, AMD’s upcoming Verano processors will continue using the 2nm process and integrate LPDDR memory. TSMC’s facility in Arizona has also been included in the roadmap for future mass production. AMD is simultaneously investing over $10 billion into Taiwan’s ecosystem, focusing on expanding advanced packaging capacity. Funding is flowing to key supply chain companies including ASE, SPIL, and PTI. Notably, PTI has completed the industry’s first validation of panel-level EFB (Elevated Fanout Bridge) 2.5D interconnect technology, responsible for enhancing the interconnect bandwidth and energy efficiency of the Venice CPU. AMD Helios rack-scale systems equipped with Venice CPUs and Instinct MI450X GPUs are currently being assembled by Sanmina, Wistron, Wistron NeWeb, and Inventec. The full platform is expected to begin multi-gigawatt-scale deployment in the second half of 2026. (Source: BlockBeats)