BlockBeats news, on June 15, according to etnews, TSMC will adopt the next-generation semiconductor packaging technology, Panel-Level Packaging (PLP), to directly compete with Samsung Electronics. PLP can significantly improve the production efficiency of AI chips, and as TSMC accelerates its preparations for mass production, a leadership battle with Samsung Electronics, which entered the market first, appears inevitable.
According to industry sources on the 15th, TSMC is building a materials, components, and equipment (MCE) supply chain to establish its PLP mass production system. TSMC is currently engaging in discussions with domestic and international MCE companies regarding equipment investments. It is reported that TSMC plans to begin PLP mass production as early as next year, a move interpreted as a substantial step toward this goal.
PLP is a technology that cuts wafers with completed circuit manufacturing into individual dies, then packages them on rectangular panels to produce finished products. It contrasts with “wafer-level packaging (WLP),” which packages chips directly on circular wafers. When packaging chips on circular wafers, the edge regions cannot be used to form dies and must be discarded—resulting in lower yield. Packaging on rectangular panels enables waste-free chip production. Using a standard 600×600 mm rectangular panel, approximately five to six times more chips can be produced compared to a mainstream 300 mm (12-inch) wafer.
Currently, Samsung Electronics holds a technological advantage in PLP. After acquiring the PLP business from Samsung Electro-Mechanics in 2019, Samsung Electronics has continuously strengthened its technical capabilities by applying the technology to mobile application processors (APs) and power management ICs (PMICs).
In contrast, TSMC had previously taken a more passive approach to PLP, as its traditional wafer-level packaging (WLP) had already established a competitive advantage in the foundry sector. However, with the explosive growth of the AI chip market, the situation has reversed—PLP can increase AI chip throughput and enable larger-area AI chips. As a result, TSMC has actively advanced its PLP business since 2024. It is expected that TSMC will build and operate a pilot production line this year, with mass production anticipated to begin around next year following performance evaluations. Reports indicate that TSMC has already secured a global AI chip customer.
As TSMC accelerates the mass production of PLP, competition with Samsung Electronics is expected to intensify. Samsung also plans to expand the application of PLP beyond its current use in APs and PMICs to high-performance computing (HPC) chips, such as AI semiconductors. Additionally, glass substrates, which have garnered significant attention as a base for AI chips, are likely to be integrated into this PLP process—signaling a coming battle for leadership in the next-generation substrate market between Samsung Electronics and TSMC.
A industry insider stated: “Not only Samsung Electronics and TSMC, but global outsourced semiconductor assembly and test (OSAT) companies are also heavily entering the PLP process market,” and added, “Intense competition is expected, while the market is also set to grow.”