Nhà khoa học Huawei cảnh báo về các giới hạn vật lý trong việc mở rộng chip AI

The Hu 火星财经 report states that on August 4, Liao Heng, Chief Scientist of Huawei's Semiconductor Division and one of the core founders of the Ascend AI chip, issued a warning in a recent public interview, stating that Western chip giants represented by NVIDIA are approaching physical limits as they pursue more powerful processors: “Expanding scale by continuously adding more computing chips and more HBM inevitably has a ceiling. The industry is still pushing forward, but once this physical limit is crossed, a collapse will occur.” Liao Heng compared the entire AI value chain to an “18-story pagoda,” aligning with NVIDIA CEO Jensen Huang’s “layered cake” framework, emphasizing that China must build collaborative capabilities at every level, particularly requiring close cooperation between chip manufacturers and AI model developers. Liao also revealed that Huawei will soon launch its first smartphone chip designed under the Tau Scaling Law framework, implemented via LogicFolding technology; after analysis by institutions such as SemiAnalysis and TechInsights, “the world will clearly understand by the end of this year how this alternative path helps narrow the gap.” Tau Scaling Law is an innovative design philosophy proposed by Huawei, focusing on enhancing transmission speeds between components in a computer system as the inherent advantages of chip miniaturization gradually diminish. Liao also highly praised Liang Wenheng, founder of DeepSeek, noting that the key to training top-tier models with extremely low compute power in 2025 lies in innovative model architecture design, comparing China’s AI innovation to maximizing space utilization in a small apartment, while Western counterparts live in much larger villas. Liao stated that Huawei itself is also developing AI chips capable of better supporting efficient architectures through co-design mechanisms between chips and models: “We must invest more effort into design to trade higher complexity for reduced computational resource consumption.”