TSMC is finally set to resume SRAM scaling with its A14 node, following a stall that began after N5, according to Korean media reports. SRAM bitcell sizes have remained at 0.021 µm² for roughly eight years since the introduction of the N5 (5 nm) process in 2020. With A14, however, the size of a high-density 6T SRAM (static random-access memory) bitcell is expected to shrink to below 0.017 µm². Korean media noted that this would put TSMC ahead of Intel’s 18A process, for which Intel reported a high-density bitcell size of 0.021 µm² and a maximum SRAM macro density of 38.1 megabits/mm² at last year’s ISSCC. SRAM is the ultrafast cache memory used inside CPUs, GPUs, and AI accelerators. Smaller bitcells—the smallest individual memory cells—allow more memory to fit into the same area, directly affecting performance and power efficiency. https://t.co/tYuy9jFUD4