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<p>Huawei reveals its path to 1.4nm chips by 2031—without ASML EUV lithography. 🧵 

At IEEE ISCAS 2026, Huawei introduced the Tau (τ) Scaling Law and LogicFolding architecture. Instead of traditional geometric shrinking, the framework stacks logic circuitry vertically to slash transmission lag and maximize transistor density. 

The architecture debuts this fall in the next-generation Kirin processors. Huawei notes it has already quietly mass-produced 381 chip models under U.S. export controls over the last 6 years, aiming for a 1.4nm-class process equivalency by 2031. 
Source: Tom's Hardware</p>

Huawei reveals its path to 1.4nm chips by 2031—without ASML EUV lithography. 🧵 
At IEEE ISCAS 2026, Huawei introduced the Tau (τ) Scaling Law and LogicFolding architecture. Instead of traditional geometric shrinking, the framework stacks logic circuitry vertically to slash transmission lag and maximize transistor density. 
The architecture debuts this fall in the next-generation Kirin processors. Huawei notes it has already quietly mass-produced 381 chip models under U.S. export controls over t

Huawei reveals its path to 1.4nm chips by 2031—without ASML EUV lithography. 🧵 At IEEE ISCAS 2026, Huawei introduced the Tau (τ) Scaling Law and LogicFolding architecture. Instead of traditional geometric shrinking, the framework stacks logic circuitry vertically to slash transmission lag and maximize transistor density. The architecture debuts this fall in the next-generation Kirin processors. Huawei notes it has already quietly mass-produced 381 chip models under U.S. export controls over the last 6 years, aiming for a 1.4nm-class process equivalency by 2031. Source: Tom's Hardware

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